• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1999.03b
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• pp.157-160
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• 1999

Aluminum 4343(filler thickness ; 10${\mu}{\textrm}{m}$/Al 3N03(core 80${\mu}{\textrm}{m}$)/Al 4343(filler 10${\mu}{\textrm}{m}$) clad sheet which is recently developed as brazing sheet materials for automotive condensers was fabricated by castinglongrightarrowhot rollinglongrightarrowcold rollinglongrightarrowintermediate annealing(IA)longrightarrowfinal cold rolling(CR). and the effect of IA/CR conditions on microstructure and sagging resistance were investigated the sheet which were fabricated by optimum conditions (IA'ed at 42$0^{\circ}C$ followed by CR'ed to 20~45%) showed good sagging resistance because the core obtained a coarsely recrystallized grain structure during brazing and consequently inhibited filled alloy penetration into the core.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.4
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• pp.555-562
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• 1990

Alloyed ohmic contact properties of Au-Zn/Au, Au-Be/Au,Au-Zn/Cr/Au, and Au-Be/Cr/Au metal system to p-InP were investigated. Optimum alloying conditions were obtained at the annealing temperature of 425\ulcorner for all the metal systems using a rapid thermal annealing system. Surface AES analysis and auger depth profiling were done for each metal system annealed at the optimum conditions. Outdiffusions of In and P from the InP substrate were found in the metal systems without Cr intermediate layer. Also, small amount of In. P and Cr were detected at the surface in the case of Au-Zn/Cr/Au system, while there were occured no outdiffusion of In, P, and Cr for Au-Be/Cr/Au system. The best surface morpholoty and specific contact resistivity of 4.5x 10**-5 \ulcornercm\ulcornerhave been obtained in this Au-Be/Cr/Au material system alloyed at 425\ulcorner for 60 second.

• Applied Microscopy
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• v.45 no.1
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• pp.16-22
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• 2015

The reaction kinetics of the growth of Ni germanide in the Ni/Zr-interlayer/Ge system was investigated using isothermal in situ annealing at three different temperatures in a transmission electron microscope. The growth rate of Ni germanide in the Ni/Zr-interlayer/Ge system was determined to be diffusion controlled and depended on the square root of the time, with the activation energy of $1.04P{\pm}0.04eV$. For the Ni/Zr-interlayer/Ge system, no intermediate or intermixing layer between the Zr-interlayer and Ge substrate was formed, and thus the Ni germanide was formed and grew uniformly due to Ni diffusion through the diffusion path created in the amorphous Zr-interlayer during the annealing process in the absence of any intermetallic compounds. The reaction kinetics in the Ni/Zr-interlayer/Ge system was affected only by the Zr-interlayer.

• Journal of the Korean Ceramic Society
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• v.33 no.10
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• pp.1101-1108
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• 1996

No-doped PZT thin films have been fabricated on Pt/Ti/SiO2/Si substrate using Sol-Gel technique. A fast annealing metho (three times of intermediate and final annealing) was used for the preparation of multi-coated 1800$\AA$ thick Nb-doped PZT thin films. As Nb doping percent was increased leakage current was lowered approximately 2 order but dielectic properties were degraded due to the appearance of pyrochlore phase and domain pinning. Futhermore the increase of the final annealing temperature up to 74$0^{\circ}C$lowered the pyrochlore phase content resulting in enhancing the dielectric properties of the Nb doped films. The 3%-Nb doped PZT thin films with 5% excess Pb showed a capacitance density of 24.04 fF/${\mu}{\textrm}{m}$2 a dielectric loss of 0.13 a switchable polarization of 15.84 $\mu$C/cm2 and a coercive field of 32.7 kV/cm respectively. The leakage current density of the film was as low as 1.47$\times$10-7 A/cm2 at the applied voltage of 1.5 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1091-1098
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• 1998

Thermal stability of the electroless deposited Cu thin film was investigated. Cu/TaN/Si multilayer was fabricated by electroless-depositing Cu thin layer on TaN diffusion barrier layer which was deposited by MOCVD on the Si substrate, and was annealed in $H_2$ ambient to investigate the microstructure of Cu film with a post heat-treatment. Cu thin film with good adhesion was successfully deposited on the surface of the TaN film by electroless deposition with a proper activation treatment and solution control. Microstructural property of the electroless-deposited Cu layer was improved by a post-annealing in the reduced atmosphere of $H_2$ gas up to $600^{\circ}C$. Thermal stability of Cu/TaN/Si system was maintained up to $600^{\circ}C$ annealing temperature, but the intermediate compounds of Cu-Si were formed above $650^{\circ}C$ because Cu element passed through the TaN layer. On the other hand, thermal stability of the Cu/TaN/Si system in Ar ambient was maintained below $550^{\circ}C$ annealing temperature due to the minimal impurity of $O_2$ in Ar gas.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.9
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• pp.76-84
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• 1992

The DSP silicon compiler consists of language compiler, module generator, placement tool, router, layout generation tools, and simulator. In this paper, The language compiler, the module generator, placement tool, and simulator were developed and provided for the system designer. The language compiler translates the designer's system description language into the intermediate form file. The intermediate form file expresses the interconnections and specifications of the cells in the cell library. The simulator was developed and provided for the behavioral verification of the DSP system. For its implementation, the event-driven technique and the C$^{++}$ task library was used. The module generator was developed for the layout of the verified DSP system, and generates the functional block to be used in the DSP chip. And then the placement tool determines the appropriate positions of the cells in the DSP chip. In this paper, the placement tool was implemented by Min-Cut and Simulated Annealing algorithm. The placement process can be controlled by the several conditions input by the system designer.

• 한국초전도학회:학술대회논문집
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• v.13
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• pp.87-87
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• 2003

• Progress in Superconductivity
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• v.9 no.2
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• pp.193-198
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• 2008

We fabricated BSCCO-2212(2212) bulk superconductors by using a casting process and evaluated the superconducting properties. The effects of annealing conditions on microstructure and critical properties were studied. It was found that the homogeneous and uniform microstructure improved the critical properties and the microstructures of ingot and annealed rods were different with the size of 2212 rod and tube. The critical current($I_c$) of rods increased with increasing annealing time, probably due to increased grain size of 2212. Annealing time of the highest $I_c$ for the smaller rod(diameter of 10 mm) was shorter(150 hr) than that of the larger rod(diameter of 16 mm, 400 hr). This size effect seems to be related to different grain sizes of the intermediate phases such as 2201 and secondary phases in the ingot. In addition, we fabricated 2212 tubes from the rod by removing the center region which contained inhomogeneous microstructures. The $I_c$ of 2212 tube with the outer diameter of 16 mm and the thickness of 2 mm was measured to 844 A, which corresponds to the critical current density of $1017\;A/cm^2$ at 77 K.

• Journal of the Korean Vacuum Society
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• v.12 no.3
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• pp.168-173
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• 2003

Recently, according to the rapid progress in Flat-panel-display industry, there has been a growing interest in the poly-Si process. Compared with a-Si, poly-Si offers significantly high carrier mobility, so it has many advantages to high response rate in Thin Film Transistors (TFT's). We have investigated a new process for the high temperature Solid Phase Crystallization (SPC) of a-Si films without any damages on glass substrates using thin film heater. because the thin film heater annealing method is a very rapid thermal process, it has very low thermal budget compared to the conventional furnace annealing. therefore it has some characteristics such as selective area crystallization, high temperature annealing using glass substrates. A 500 $\AA$-thick a-Si film was crystallized by the heat transferred from the resistively heated thin film heaters through $SiO_2$ intermediate layer. a 1000 $\AA$-thick $TiSi_2$ thin film confined to have 15 $\textrm{mm}^{-1}$ length and various line width from 200 to 400 $\mu\textrm{m}$ was used as the thin film heater. By this method, we successfully crystallized 500 $\AA$-thick a-Si thin films at a high temperature estimated above $850^{\circ}C$ in a few seconds without any thermal deformation of g1ass substrates. These surprising results were due to the very small thermal budget of the thin film heaters and rapid thermal behavior such as fast heating and cooling. Moreover, we investigated the time dependency of the SPC of a-Si films by observing the crystallization phenomena at every 20 seconds during annealing process. We suggests the individual managements of nucleation and grain growth steps of poly-Si in SPC of a-Si with the precise control of annealing temperature. In conclusion, we show the SPC of a-Si by the thin film heaters and many advantages of the thin film heater annealing over other processes

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.6
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• pp.448-453
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• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.