• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.377-378
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• 2012

DC-DC 컨버터를 인터리브 방식으로 제어하면 출력 전류 리플이 저감되고, 출력 필터 커패시터의 용량을 줄일 수 있다. 하지만 공진(Resonance)을 통해 전력을 전달하는 LLC 공진형 컨버터의 경우 회로를 구성하는 공진 인덕터 및 공진 커패시터의 오차(Tolerance)로 인해 출력 전류 리플의 언밸런스가 심화될 수 있다. 따라서 이를 개선할 수 있는 방법에 대한 연구가 필요하다. 본 논문에서는 Y결선 정류기를 이용한 3상 인터리브드 LLC 공진형 컨버터의 출력 전류 리플 밸런싱 방법을 제안한다. 제안된 방법은 3상 인터리브드 LLC 공진형 컨버터와 각 LLC 공진형 컨버터 앞단의 Bridgeless PFC가 독립적으로 추가되어 회로가 구성된다. 3상 인터리브드 LLC 공진형 컨버터는 분할된 위상으로 비독립적으로 제어하며 출력 전류 리플의 언밸런스를 Bridgeless PFC의 출력 전압을 가변함으로써 개선할 수 있는 방법을 제안하고 이를 시뮬레이션(PSIM)을 통해 제안된 밸런싱 방법을 검증하였다.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.629-638
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• 2016

This paper proposes a State-of-Charge (SOC) balancing control of Battery Power Modules (BPMs) for a modularized battery for Electric Vehicles (EVs) without additional balancing circuits. The BPMs are substituted with the single converter in EVs located between the battery and the inverter. The BPM is composed of a two-phase interleaved boost converter with battery modules. The discharge current of each battery module can be controlled individually by using the BPM to achieve a balanced state as well as increased utilization of the battery capacity. Also, an SOC balancing method is proposed to reduce the equalization time, which satisfies the regulation of a constant DC-link voltage and a demand of the output power. The proposed system and the SOC balancing method are verified through simulation and experiment.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.