• Journal of the Korean institute of surface engineering
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• v.36 no.1
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• pp.74-78
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• 2003

The corrosion failure of electronic devices has been a major reliability concern lately. This failure is an ongoing concern because of miniaturization of integrated circuits (IC) and the increased use of polymers in electronic packaging. Recently, plasma-polymerized cyclohexane films were considered as a possible candidate for a interlayer dielectric for multilever metallization of ultra large scale integrated (ULSI) semiconductor devices. In this paper the protective ability of above films as a function of deposition temperature and RF power in an 3.5 wt.% NaCl solution were examined by polarization measurement. The film was characterized by FTIR spectroscopy and contact angle measurement. The protective efficiency of the film increased with increasing deposition temperature and RF power, which induced the higher degree of cross-linking and hydrophobicity of the films.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.12
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• pp.192-199
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• 2001

Chemical mechanical planarization (CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There hale been serious problems in CMP in terms of repeatability and deflects in patterned wafers. Especial1y, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using CeO$_2$is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method fur developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.87-91
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• 2024

SiO₂, renowned for its excellent insulating properties, has been used in the semiconductor industry as a valuable dielectric material. High-quality SiO₂ films find applications in gate spacers and interlayer insulation gap-fill oxides, among other uses. One of the prevalent methods for depositing these SiO₂ films is plasma enhanced chemical vapor deposition (PECVD) favored for its relatively low processing costs and ability to operate at low temperatures. However, compared to the increasingly utilized atomic layer deposition (ALD) method, PECVD exhibits inferior film characteristics such as uniformity. This study aims to produce SiO₂ films with uniformity as close as possible to those achieved by ALD through the adjustment of PECVD process parameters. we conducted a total of nine PECVD processes, varying the process time and gas flow rates, which were identified as the most influential factors on the PECVD process. Furthermore, ellipsometry analysis was employed to examine the uniformity variations of each process. The experimental results enabled us to elucidate the relationship between uniformity and deposition rate, as well as the impact of gas flow rate and deposition time on the process outcomes. Additionally, thickness measurements obtained through ellipsometer facilitate the identification of optimal process parameters for PECVD.

• Journal of the Korean Vacuum Society
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• v.6 no.4
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• pp.326-336
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• 1997

From the concept that the ion implantation-induced defect is one of the major factors in determining source/drain junction characteristics, high quality ultra-shallow $p^+$-n junctions were formed through the control of ion implantation-induced defects in silicon substrate. In conventional process of the junction formation. $p^+$ source/drain junctions have been formed by $^{49}BF_2^+$ ion implantation followed by the deposition of TEOS(Tetra-Ethyl-Ortho-Silicate) and BPSG(Boro-Phospho-Silicate-Glass) films and subsequent furnace annealing for BPSG reflow. Instead of the conventional process, we proposed a series of new processes for shallow junction formation, which includes the additional low temperature RTA prior to furnace annealing, $^{49}BF_2^+/^{11}B^+$ mixed ion implantation, and the screen oxide removal after ion implantation and subsequent deposition of MTO (Medium Temperature CVD oxide) as an interlayer dielectric. These processes were suggested to enhance the removal of ion implantation-induced defects, resulting in forming high quality shallow junctions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.615-618
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• 2004

The piezoelectricity and polarization of multilayer ceramic actuators, being designed to stack ceramic layer and electrode layer alternately, were investigated under a consideration of geometry, the thickness ratio of the ceramic layer to electrode layer The actuators were fabricated by tape-casting of $0.42PbTiO_3-0.38PbZrO_3-0.2Pb(Mn_{1/3}Nb_{2/3})O_3$ followed by laminating, burn-out and co-firing process. The actuators of $5\times5mm^2$ in area were formed in a way that $60{\sim}200{\mu}m$ thick ceramics were stacked 10 times alternately with $5{\mu}m$ thick electrode. Increase in polarization and electric field-displacement with increasing thickness ratio of the ceramic/electrode layer and thickness/cross section ratio were attributed to the change of $non-180^{\circ}/180^{\circ}$ domain ratio which was affected by the interlayer internal stress and Poisson ratio of ceramic layer. The piezoelectricity and actuation behaviors were found to be dependent upon the volume ratio (or thickness ratio) of ceramic layer relative to ceramic layer. Concerning with the existence of internal stress, the field-induced polarization and deformation were described in the multilayer actuator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.10
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• pp.1049-1055
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• 2004

Chemical Mechanical Polishing (CMP) is referred to as a three body tribological system, because it includes two solids in relative motion and the CMP slurry. On the assumption that the abrasives between the pad and the wafer could be a major reason not only for the friction force but also for material removal during polishing, the friction force generated during CMP process was investigated with the change of abrasive size and concentration of CMP slurry. The threshold point of average coefficient of friction (COF) with increase in abrasives concentration during interlayer dielectric (ILD) CMP was found experimentally and verified mathematically based on contact mechanics. The predictable models, Mode I (wafer is in contact with abrasives and pad) and Mode II (wafer is in contact with abrasives only), were proposed and used to explain the threshold point. The average COF value increased in the low abrasives concentration region which might be explained by Mode I. In contrast the average COF value decreased at high abrasives concentration which might be regarded to as Mode II. The threshold point observed seemed to be due to the transition from Mode I to Mode II. The tendency of threshold point with the variation of abrasive size was studied. The increase of particle radius could cause contact status to reach transition area faster. The correlation between COF and material removal rate was also investigated from the tribological and energetic point of view. Due to the energy loss by vibration of polishing equipment, COF value is not proportional to the material removal rate in this experiment.

• Korean Journal of Materials Research
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• v.10 no.6
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• pp.450-455
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• 2000

For further scaling down of the silicon devices, the application of low dielectric constant materials instead of silicon oxide has been considered to reduce power consumption, crosstalk, and interconnection delay. In this paper, the effect of $O_2/SF_6$ plasma chemistry on the etching characteristics of polyimide-one of the promising low-k interlayer dielectrics-has been studied. The etch rate of polyimide decreases with the addition of $SF_6$ gas due to formation of nonvolatile fluorine compounds inhibiting reaction between oxygen and hydrocarbon polymer, while applying substrate bias enhances etching process through physical attack. However, addition of small amount of $SF_6$ is desirable for etching topography. $SiO_2$ hard mask for polyimide etching is effective under $O_2$plasma etching(selectivity~30), while $O_2/SF_6$ chemistry degrades etching selectivity down to 4. Based on the above results, $1-2\mu\textrm{m}$ L&S PI2610 patterns were successfully etched.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.118-118
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• 2008

The oxide CMP has been applied to interlayer dielectric(ILD) and shallow trench isolation (STI) in chip fabrication. Recently the slurry used in oxide CMP being changed from silica slurry to ceria (cerium dioxide) slurry particularly in STI CMP, because the material selectivity of ceria slurry is better than material selectivity of silica slurry. Moreover, the ceria slurry has good a planarization efficiency, compared with silica slurry. However ceria abrasives make a material removal rate too high at the region of wafer center. Then we focuses on why profile of material removal rate is convex. The material removal rate sharply increased to 3216 $\AA$/min by $4^{th}$ run without conditioning. After $4^{th}$ run, material removal rate converged. Furthermore, profile became more convex during 12 run. And average material removal rate decreased when conditioning process is added to end of CMP process. This is due to polishing mechanism of ceria. Then the ceria abrasive remains at the pad, in particular remains more at wafer center contacted region of pad. The field emission scanning electron microscopy (FE-SEM) images showed that the pad sample in the wafer center region has a more ceria abrasive than in wafer outer region. The energy dispersive X-ray spectrometer (EDX) verified the result that ceria abrasive is deposited and more at the region of wafer center. Therefore, this result may be expected as ceria abrasives on pad surface causing the convex profile of material removal rate.