• Title/Summary/Keyword: Interface Program

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Posttraumatic Stiffness (외상 후 동결견)

  • Choi, Chang-Hyeok
    • Clinics in Shoulder and Elbow
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    • v.9 no.1
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    • pp.14-19
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    • 2006
  • The patient with a posttraumatic stiffness frequently has a history of prolonged immobilization after a traumatic event. Adhesions in the extraarticular humeroscapular motion interface may be present independently or in combination with intraarticular capsular contractures. A through history and physical examination usually reveal the cause and anatomic location of stiffness. Passive stretching exercise program is effective as a first line treatment, but manipulation under anesthesia is usually not effective because of potential complication such as fracture, tendon rupture and neurologic injury. The humeroscapular motion interface adhesion can be released either open or arthroscopically. The combined technique coupled with an aggressive rehabilitation program can provide more effective motion restoration and pain relief.

A Study on Development of Automatic Weld-Seam Tracking System using Vision Sensor (시각센서를 이용한 용접선 자동추적시스템의 개발에 관한 연구)

  • 배강열;이지형
    • Journal of Welding and Joining
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    • v.14 no.4
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    • pp.79-88
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    • 1996
  • For improvement in productivity and weld quality, weld seam tracking and welding parameter control are very essential in the welding of a structure which can not be cxactly fit-up due to mismatch, discontinous gap, deflection, etc.. In this study, an automatic weld seam tracking system is developed for I-butt joint structure, and the system consists of XYZ working table, vision sensor and user interface program. In the developed vision sensor system, an image projection algorithm for weld-line detection and an adaptive current control algorithm for gap variation were implemented. The user interface program developed in this study by basing on the objct oriented concept could provide very convenient way to utilize the tracking system with the pull-down menu driven structure. The developed system showed a good seam tracking and weld quality control capability corresponding to deflected weld lines and gap variations.

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Prototyping Training Program in Immersive Virtual Learning Environment with Head Mounted Displays and Touchless Interfaces for Hearing-Impaired Learners

  • HAN, Insook;RYU, Jeeheon;KIM, Minjeong
    • Educational Technology International
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    • v.18 no.1
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    • pp.49-71
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    • 2017
  • The purpose of the study was to identify key design features of virtual reality with head-mounted displays (HMD) and touchless interface for the hearing-impaired and hard-of-hearing learners. The virtual reality based training program was aimed to help hearing-impaired learners in machine operating learning, which requires spatial understanding to operate. We developed an immersive virtual learning environment prototype with an HMD (Oculus Rift) and a touchless natural user interface (Leap Motion) to identify the key design features required to enhance virtual reality for the hearing-impaired and hard-of-hearing learners. Two usability tests of the prototype were conducted, which revealed that several features in the system need revision and that the technology presents an enormous potential to help hearing-impaired learners by providing realistic and immersive learning experiences. After the usability tests of hearing-impaired students' exploring the 3D virtual space, interviews were conducted, which also established that further revision of the system is needed, which would take into account the learners' physical as well as cognitive characteristics.

Development of the Buckling Strength Assessment System based on Offshore Structure Design Code (해양구조물 설계코드에 기반한 좌굴강도 평가 시스템 개발)

  • Kim, Ul-Nyeon
    • Special Issue of the Society of Naval Architects of Korea
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    • 2017.10a
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    • pp.38-45
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    • 2017
  • FPSO is widely used to develop deep sea oil fields and HHI has constructed ten(10) FPSOs. During these constructions, relevant structural design criteria such as yielding, buckling, fatigue, collision and impact strength were applied to verify structural safety. To apply the buckling strength evaluation for structures, the critical buckling stresses and applied stresses of relevant panels should be calculated. The plate and stiffened panels are to be idealized, which are needed much time and efforts by designers. Therefore, program development is necessary in order to evaluate the buckling strength conveniently and accurately. In this study, the buckling strength assessment system by using offshore code, DNV-RP-C201 was developed under MSC/PATRAN, pre-post program of finite element method. Graphic user interface program is written in MSC/PATRAN PCL functions. Source program to evaluate the buckling strength is developed in FORTRAN programming languages. The developed program is verified by comparing with the results of the Nauticus Hull developed by DNV Classification Society, and applied to the marine construction project conducted by Hyundai Heavy Industries LTD.

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A New Programming Method of Scaled SONOS Flash Memory Ensuring 1$\times$10$^{6}$ Program/Erase Cycles and Beyond (1x10$^{6}$ 회 이상의 프로그램/소거 반복을 보장하는 Scaled SONOS 플래시메모리의 새로운 프로그래밍 방법)

  • 김병철;안호명;이상배;한태현;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.54-57
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    • 2002
  • In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

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Development of Multi Layered Elastic Pavement Analysis Program Package Considering Temperature Nonlinearty of Asphalt Layer on GUI Environment (아스팔트층 온도 비선형성을 고려한 사용자 편의환경의 다층탄성 프로그램 개발)

  • Choi, Jun-Seong;Seo, Joo-Won;Park, Keun-Bo;Kim, Soo-Il
    • International Journal of Highway Engineering
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    • v.10 no.4
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    • pp.91-101
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    • 2008
  • A multi layered elastic analysis program, IDYSPAP, was developed. The objective of this study was to develop the IDYSPAP program on Graphic User Interface environment for field engineers using Visual Basic, which was considered span of multi-wheels and maximum 4 axles using superposition of linear elastic theorem. It is suggested that this study considers algorithm with dynamic properties of asphalt layer on various temperature and non-linear properties of subbase and subgrade on stress non-linearity for asphalt pavement structure. This Program was modified to divide asphalt layer automatically according to layer division concept. The developed program was verified with initial measuring data in test road sections of KEC (Korea Expressway Co.) using laboratory test results.

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The Improved Electrical Endurance(Program/Erase Cycles) Characteristics of SONOS Nonvolatile Memory Device (SONOS 비휘발성 기억소자의 향상된 프로그램/소거 반복 특성)

  • 김병철;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.1
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    • pp.5-10
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    • 2003
  • In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

The Design of High Speed Processor for a Sequence Logic Control using FPGA (FPGA를 이용한 시퀀스 로직 제어용 고속 프로세서 설계)

  • Yang, Oh
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.12
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    • pp.1554-1563
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    • 1999
  • This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

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The Communication Method at the Auto-Startup System using TCP/IP and VXI and Expert System(G2)

  • Kim, Jung-Soo;Joon Lyon
    • Transactions on Control, Automation and Systems Engineering
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    • v.1 no.2
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    • pp.141-146
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    • 1999
  • This paper describes the communication method of an auto-startup system. The Auto-Startup system is designed to operate a nuclear power plant automatically during the startup operation . In general , the operations during startup in existing plant have only been manually controlled by the operator. The manual operation caused to the operator mistake. The Auto-Startup system consists of the Distributed Control System(DCS) and G2 (Expert System). Also, Functional Test Facility(FTF) provides the plant's real-data for an Auto-Startup system. So, it is necessary to develop the communication method between these systems. We developed two methods ; one is a network and the other is a hardwire line. To communicate between these systems (DCS-G2 and DCS-FTF) , we developed the communication program. In case of DCS-FTF, we used the TCP/IP and VXI. BUt, in case of DCS-G2 , we , what it called , developed the bridge program using the GSI(G2 Standard Interface). We test to check the function of the important parameter, in time, for analysis of the developed communication method. The results are a good performance when we check the communication time of important parameter. We conclude that Auto-startup system could save heat-up time about at least 5 hours and reduced the change of the reactor operation and trip.

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An Experimental Study of Private Key and Secret Key Disclosure Vulnerability in Cryptographic Service Provider(CSP) Module (Cryptographic Service Provider(CSP) 모듈의 개인키/비밀키 노출 취약점에 대한 실험적 연구)

  • Park, Jin-Ho;Cho, Jae-Ik;Im, Eul-Gyu
    • Convergence Security Journal
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    • v.7 no.3
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    • pp.61-70
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    • 2007
  • In Windows operating system, CSPs(Cryptographic Service Providers) are provided for offering a easy and convenient way of using an various cryptographic algorithms to applications. The applications selectively communicate with various CSPs through a set of functions known as the Crypto API(Cryptographic Application Program Interface). During this process, a secure method, accessing data using a handle, is used in order to prevent analysis of the passing parameters to function between CryptoAPI and CSPs. In this paper, our experiment which is using a novel memory traceback method proves that still there is a vulnerability of private key and secret key disclosure in spite of the secure method above-mentioned.

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