• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.414-416
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• 2004

The intelligent PVR(Personal Video Recorder) is an enhanced PVR that provides viewers with some advanced features as well as pause, instant replay, search and skip forward found in conventional PVRs. By embedding a home server into a PVR, it is possible for an intelligent PVR to provide a powerful web-based management user interface constructed using HTML, graphics and other features common to web-browsers. When applied to other embedded systems, web technologies offer graphical user interfaces which are user-friendly, inexpensive, cross-platform and network-ready. It is the purpose of this paper to introduce implementation of intelligent PVR which is control by internet. We present the architecture of an home- server with a simple but powerful web-based network interconnection.

• Journal of the Korean Institute of Intelligent Systems
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• v.8 no.5
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• pp.61-71
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• 1998

Genetic Algorithm(GA) is a method of approaching optimization problems by modeling and simulating the biological evolution. GA needs large time-consuming, so ti had better do on a parallel computer architecture. Our proposed system has a VLSI-oriented interconnection network, which is constructed from a viewpoint of fractal geometry, so that self-similarity is considered in its configuration. The approach to Parallel Genetic Algorithm(PGA) on our proposed system is explained, and then, we construct the classifier system such that the set of samples is classified into weveral classes based on the features of each sample. In the process of designing the classifier system, We have applied PGA to the Traveling Salesman Problem and classified the sample set in the Euclidean space into several categories with a measure of the distance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.59-66
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• 1997

Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.451-458
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• 2013

This paper describes a design of LIN MCU using efficient memory accessing architecture which provides concurrent data and address fetch for faster communication. By using slew rate control it can reduce EMI emission while satisfying required communication specifications. To verify the efficiency of the LIN MCU, we developed a SoC and tested for several data packets. Measurements show that this LIN MCU improves network efficiency up to 17.19 % and response time up to 31.26 % for nominal cases. EMI radiation also can be reduced up to 10 dB.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.17 no.3
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• pp.70-77
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• 2009

We proposed the method of avionics integrated architecture using high-speed fiber optic bus. Typically, data bus of aircraft consists of electronic and optic data transmission method. Avionics systems are difficult to operate the electronic data transmission method for the high speed data processing, synchronization and interconnection between flight control system and flight management system efficiently. In this paper, it is known to look into the problem of data bus and the advanced trend in avionics systems, and propose the appropriate data bus of the advanced avionics systems.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.165-180
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• 1997

일반 병렬 처리 시스템(General Purpose Multiprocessors)과는 달리, 병렬 트랜잭션(Transaction) 처리 시스템의 성능은 메모리의 계층구조와 입출력 시스템의 구조 등에 크게 영향을 받는 특징을 갖는다. 본 논문은 입출력 노드의 성능 분석에 주안점을 두고 전제 시스템에서의 입출력 노드의 개수, 병렬 디스크의 개수 및 상호연결망(Interconnection Network)과의 접속을 제공하는 스위치의 처리 용량 등의 인수들이 SPAX 병렬 트랜잭션처리 시스템의 미치는 성능의 평가 및 분석에 대한 연구 내용 기술한다. 본 연구에서는 벤치마크로는 병렬 트랜잭션 시스템의 성능 평가에 주로 사용되고 있는 TPC-C 벤치마크를 사용하며 모의 입력(Synthetic workload)을 통한 성능분석을 수행하였다. 본 연구는 입출력노드에 부하가 많이 걸릴 경우 패킷의 크기에 따라 시스템의 성능에 큰 영향을 미치며, 반면에 입출력 노드내의 상호연결망의 접속(Interface)을 제공하는 XNIF의 데이터 버퍼 개수의 증가는 시스템의 성능 향상에 기여를 하지 않음을 보여준다. 이는 시스템의 성능향상을 위해서는 패킷 전송 경로상의 모든 시스템 요소의 성능 향상이 병행되어야 함을 보여준다. 마지막으로 프로세싱노드와 입출력노드의 처리능력의 균형이 병렬 트랜잭션 시스템의 설계에 있어서 매우 중요함을 보여준다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.140-150
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• 1995

A symbolic layout generator, called Flexible Module Generator (FMG), has been developed for transgorming a given CMOS circuit netlist into an optimized symbolic layout. Contrary to other conventional module generators which place transistors either in horizontal or in vertical direction, FMG places transittors in any hence can multiples of 90$^{\circ}$. This flexible layout style can maximize the diffusion sharing and hence can reduce the wire-length for both of area minimization and performance improvement. In FMG, transistors are initially randomly placed and then selected transistors are iteratively replaced using an optimization technique based on simulated evolution. Whenever a transistor is replaced, the affected nets are rerouted. Constraints on the shape, aspect ratio, and critical path delays are considered during the optimization process. Routing is performed by using a modified maze router on polysilicon, metal 1, and metal 2 interconnection layers. additional routing grids are added, if necessary, for complete routing. Unused rows or columns are removed after routing for area minimization. Experimental reasults show that FMG synthesizes satisfactory layouts.

• Journal of the Korea Society for Simulation
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• v.6 no.2
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• pp.89-104
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• 1997

Performance bottleneck of parallel computer systems has mostly been I/O devices because of disparity between processor speed and I/O speed. Therefore I/O node placement strategy is required such that it can minimize the number of I/O nodes, I/O access time and I/O traffic in an interconnection network. In this paper, we propose an optimal distance-k embedding algorithm, and analyze its effect on system performance when this algorithm is applied to n x n torus architecture. We prove this algorithm is an efficient I/O node placement using software simulation. I/O node placement using the proposed algorithm shows the highest performance among other I/O node placements in all cases. It is because locations of I/O nodes are uniformly distributed in the whole network, resulting in reduced traffic in the intE'rconnection network.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.438-451
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• 1994

A low complexity, fault detecting computer architecture for utilisation in programmable logic controllers is designed. The cyclic operating mode of PLCs and a specification level, graphical programming paradigm based on the interconnection of application oriented standard software function modules are architecturally supported. Thus, by design, there is no semantic gap between the programming and machine execution levels enabling the safety licensing of application software by an extremely simple, but rigorous method, viz, diverse back translation.

• Journal of Communications and Networks
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• v.14 no.2
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• pp.213-221
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• 2012

The architecture of an interconnection network is usually represented by a graph, and a graph G is bipancyclic if it contains a cycle for every even length from 4 to ${\mid}V(G){\mid}$. In this article, we analyze the conditional edge-fault-tolerant properties of an enhanced hypercube, which is an attractive variant of a hypercube that can be obtained by adding some complementary edges. For any n-dimensional enhanced hypercube with at most (2n-3) faulty edges in which each vertex is incident with at least two fault-free edges, we showed that there exists a fault-free cycle for every even length from 4 to $2^n$ when n($n{\geq}3$) and k have the same parity. We also show that a fault-free cycle for every odd length exists from n-k+2 to $2^n-1$ when n($n{\geq}2$) and k have the different parity.