• Title/Summary/Keyword: Integrated circuit processing

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A 2.4 GHz Bio-Radar System with Small Size and Improved Noise Performance Using Single Circular-Polarized Antenna and PLL (하나의 원형 편파 안테나와 PLL을 이용하여 소형이면서도 개선된 잡음 성능을 갖는 2.4 GHz 바이오 레이더 시스템)

  • Jang, Byung-Jun;Park, Jae-Hyung;Yook, Jong-Gwan;Moon, Jun-Ho;Lee, Kyoung-Joung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.12
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    • pp.1325-1332
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    • 2009
  • In this paper, we design a 2.4 GHz bio-radar system that can detect human heartbeat and respiration signals with small size and improved noise performance using single circular-polarized antenna and phase-locked loop. The demonstrated bio-radar system consists of single circular-polarized antenna with $90^{\circ}$ hybrid, low-noise amplifier, power amplifier, voltage-controlled oscillator with phase-locked loop circuits, quadrature demodulator and analog circuits. To realize compact size, the printed annular ring stacked microstrip antenna is integrated on the transceiver circuits, so its dimension is just $40\times40mm^2$. Also, to improve signal-to-noise-ratio performance by phase noise due to transmitter leakage signal, the phase-locked loop circuit is used. The measured results show that the heart rate and respiration accuracy was found to be very high for the distance of 50 cm without the additional digital signal processing.

Influence of Co-sputtered HfO2-Si Gate Dielectric in IZO-based thin Film Transistors (HfO2-Si의 조성비에 따른 HfSiOx의 IZO 기반 산화물 반도체에 대한 연구)

  • Cho, Dong Kyu;Yi, Moonsuk
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.98-103
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    • 2013
  • In this work, we investigated the enhanced performance of IZO-based TFTs with $HfSiO_x$ gate insulators. Four types of $HfSiO_x$ gate insulators using different diposition powers were deposited by co-sputtering $HfO_2$ and Si target. To simplify the processing sequences, all of the layers composing of TFTs were deposited by rf-magnetron sputtering method using patterned shadow-masks without any intentional heating of substrate and subsequent thermal annealing. The four different $HfSiO_x$ structural properties were investigated x-ray diffraction(XRD), atomic force microscopy(AFM) and also analyzed the electrical characteristics. There were some noticeable differences depending on the composition of the $HfO_2$ and Si combination. The TFT based on $HfSiO_x$ gate insulator with $HfO_2$(100W)-Si(100W) showed the best results with a field effect mobility of 2.0[$cm^2/V{\cdot}s$], a threshold voltage of -0.5[V], an on/off ratio of 5.89E+05 and RMS of 0.26[nm]. This show that the composition of the $HfO_2$ and Si is an important factor in an $HfSiO_x$ insulator. In addition, the effective bonding of $HfO_2$ and Si reduced the defects in the insulator bulk and also improved the interface quality between the channel and the gate insulator.

Implementation of Multiple-Valued Adder and Multiplier Using Current-Mode CMOS (전류모드 CMOS에 의한 다치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • The KIPS Transactions:PartA
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    • v.11A no.2
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    • pp.115-122
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    • 2004
  • In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

IPv6 Migration, OSPFv3 Routing based on IPv6, and IPv4/IPv6 Dual-Stack Networks and IPv6 Network: Modeling, and Simulation (IPv6 이관, IPv6 기반의 OSPFv3 라우팅, IPv4/IPv6 듀얼 스택 네트워크와 IPv6 네트워크: 모델링, 시뮬레이션)

  • Kim, Jeong-Su
    • The KIPS Transactions:PartC
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    • v.18C no.5
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    • pp.343-360
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    • 2011
  • The objective of this paper is to analyze and characterize to simulate routing observations on end-to-end routing circuits and a ping experiment of a virtual network after modeling, such as IPv6 migration, an OSPFv3 routing experiment based on an IPv6 environment, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing using IPv6 planning and operations in an OPNET Modeler. IPv6 deployment based largely on the integrated wired and wireless network was one of the research tasks at hand. The previous studies' researchers recommended that future research work be done on the explicit features of both OSPFv3 and EIGRP protocols in the IPv4/IPv6 environment, and more research should be done to explore how to improve the end-to-end IPv6 performance. Also, most related work was performed with an IPv4 environment but lacked studies related to the OSPFv3 virtual network based on an end-to-end IPv6 environment. Hence, this research continues work in previous studies in analyzing IPv6 migration, an OSPFv3 routing experiment based on IPv6, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing. In the not too distant future, before enabling the default IPv6, it would help to understand network design and deployment based on an IPv6 environment through IPv6 planning and operations for the end-user perspective such as success or failure of connection on IPv6 migration, exploration of an OSPFv3 routing circuit based on an end-to-end IPv6 environment, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing. We were able to observe an optimal route for modeling of an end-to-end virtual network through simulation results as well as find what appeared to be a fast ping response time VC server to ensure Internet quality of service better than an HTTP server.