• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.8
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• pp.675-685
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• 2016

A research area on liquid rocket engine has been suggested. Downsizing through combustion pressure rise and low price are major issues to gas generator cycle engines. A very high pressure turbopump and material against oxidizer rich environment may be necessary technologies for staged combustion cycle engines. Integrated analysis saving computing time is the trend of rocket engine systems analysis area. Other important research topics are the methane engine for reusable booster to reduce the cost, 3D printing and materials for high temperature or oxidizer rich environment.

• Journal of Astronomy and Space Sciences
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• v.12 no.1
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• pp.78-89
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• 1995

We solved n-body problem about 9 planets, moon, and 4 minor planets with relativistic effect related to the basic equation of motion of the solar system. Perturbations including flgure potential of the earth and the moon and solid earth tidal effect were considered on this relativistic equation of motion. The orientations employed precession and nutation for the earth, and lunar libration model with Eckert's lunar libration model based on J2000.0 were used for the moon. Finally, we developed heliocentric ecliptic position and velocity of each planet using this software package named the SSEG (Solar System Ephemerides Generator) by long-term (more than 100 years) simulation on CRAY-2S super computer, through testing each subroutine on personal computer and short-time(within 800 dyas) running on SUN3/280 workstation. Epoch of input data JD2440400.5 were adopted in order to compare our results to the data archived from JPL's DE 200 by Standish and Newhall. Above equation of motion was integrated numerically having 1-day step-size interval through 40,000 days (about 110 years long) as total computing interval. We obtained high-precision ephemerides of the planets with maximum error, less $than\pm2\times10^{-8}AU(\approx\pm3km)$ compared with DE200 data (except for mars and moon).

• Nuclear Engineering and Technology
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• v.48 no.5
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• pp.1184-1191
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• 2016

This paper introduces the development of a transient monitoring system to detect the early stage of a transient, to identify the type of the transient scenario, and to inform an operator with the remaining time to turbine trip when there is no operator's relevant control. This study focused on the transients originating from a secondary system in nuclear power plants (NPPs), because the secondary system was recognized to be a more dominant factor to make unplanned turbine-generator trips which can ultimately result in reactor trips. In order to make the proposed methodology practical forward, all the transient scenarios registered in a simulator of a 1,000 MWe pressurized water reactor were archived in the transient pattern database. The transient patterns show plant behavior until turbine-generator trip when there is no operator's intervention. Meanwhile, the operating data periodically captured from a plant computer is compared with an individual transient pattern in the database and a highly matched section among the transient patterns enables isolation of the type of transient and prediction of the expected remaining time to trip. The transient pattern database consists of hundreds of variables, so it is difficult to speedily compare patterns and to draw a conclusion in a timely manner. The transient pattern database and the operating data are, therefore, converted into a smaller dimension using the principal component analysis (PCA). This paper describes the process of constructing the transient pattern database, dealing with principal components, and optimizing similarity measures.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Journal of the Korea Convergence Society
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• v.10 no.1
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• pp.13-24
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• 2019

Each company has different business processes. Since it is impossible that an ERP system contains every different business processes, the productivity of customizing and maintenance well-matched for the business process of a company is the key to successful implementation. This ERP UI development tool was developed for better connection to back-end in terms of customizing and maintenance, integration with design, providing various tools for higher productivity, reusability, and standardized user interface so that it enhances the productivity, meets the UI standard, and copes with upcoming changes of business process. In the further study, the study on the service automation and integrated development environment with front-end and back-end providing through the advanced user convenience development for front-end designer and front-end generator would be carried out.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.219-220
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• 2016

A power management system (PMS) has been an important part in a ship integrated control system. To evaluate a PMS for a liquefied natural gas carrier (LNGC), this research proposes a real-time hardware-in-the-loop simulation (HILS), which is composed of major component models such as turbine generator, diesel generator, governor, circuit breaker, and 3-phase loads on MATLAB/Simulink. In addition, FPGA based control console and main switchboard (MSBD) are constructed in order to develop an efficient control and a similar real environment in an LNGC PMS. A comparative study on the performance evaluation of PMS functions is conducted using two test cases for sharing electric power to consumers in an LNGC. The result shows that the proposed system has a high verification capability for the operating function and failure insertion evaluation as a PMS simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.71-79
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• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.7
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• pp.761-768
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• 2010

This paper presents an effective method to achieve the wideband waveform for high resolution SAR(Synthetic Aperture Radar) using the frequency multiplication technique. And also this paper analyzes the root causes for the spectral regrowth due to 3rd-order intermodulation in chirp bandwidth expansion scheme using quadrature modulator and frequency multipliers. The amplitude and phase imbalance requirement are defined based on the simulation results in terms of quadrature channel imbalance. This minimizes the degradation of range resolution, peak sidelobe ratio and integrated sidelobe ratio. The wideband chirp generator using the frequency multiplier and memory map scheme was manufactured and the compensation technique was presented to reduce the spectral regrowth of SAR waveform by minimizing the amplitude and phase imbalance. After I and Q channel imbalance adjustment, the carrier level reduces －28.7 dBm to －53.4 dBm. Chirp signal with 150 MHz bandwidth at S-band expands to 600 MHz bandwidth at X-band. The sidelobe levels are reduced by about 8 to 9 dB by compensating the amplitude balance between I and Q channels.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.55-60
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• 2005

A V-band MIMIC quadruple subharmonic mixer is reported in this paper. The cascode harmonic generator is proposed for a high conversion gain. The proposed cascode harmonic generator is shown with a 4-th harmonic output characteristic that represents an average of 2.9 dB and a maximum of 4 dB higher than the conventional multiplier. The measured result of the subharmonic mixer has a conversion gain of 3_4 dB which a good conversion gain at a LO power of 13 dBm. Isolations of LO-to-IF and LO-to-RF were obtained -53.6 dB and -46.2 dB, respectively. The conversion gain of the subharmonic mixer in this study has a higher conversion gain compared with some other reports in millimeter-wave range.