• 제어로봇시스템학회:학술대회논문집
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• 1998.10a
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• pp.14-19
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• 1998

In this paper, a target approachable force-guided control with adaptive accommodation for the complex assembly is presented. The complex assembly (CA) is defined as a task which deals with complex shaped parts including concavity or whose environment is so complex that unexpected contacts occur frequently during insertion. CA tasks are encountered frequently in the field of the manufacturing automation and various robot applications. To make CA successful, both the bounded wrench condition and the target approachability condition should be satisfied simultaneously during insertion. By applying the convex optimization technique, an optimum target approaching twist can be determined at each instantaneous contact state as a global minimum solution. Incorporated with an admissible perturbation method, a new CA algorithm using only the sensed resultant wrench and the target twist is developed without motion planning nor contact analysis which requires the geometry of the part and the environment. Finally, a VME-bus based real-time control system is built to experiment various CA task. T-insertion task as a planar CA and double-peg assembly task as a spacial assembly were successfully executed by implementing the new force-guided control with adaptive accommodation.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.815-820
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• 1998

A new coding algorithm which has spectrum notches at the DC and Nyquist Frequency for maximizing the effect of the in-band pilot insertion in order to make the symbol timing or carrier recovery easy is proposed. It is shown that this algorithm uses one encoder and gives the similar spectrum characteristics to that of the existing OF00 code which uses two encoder. In this paper, the proposed new coding algorithm is explained andits spectrum characteristics is compared with the of OF00 code using computer simulation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.577-580
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• 2004

Our paper focus on crosstalk noise problem, especially crosstalk glitch that occurs when victim is stable state and aggressor is transitive state. This generated glitch weigh with the functional reliability if the glitch is considerable. In this paper, we use buffer insertion, down sizing, buffer insertion with up-sizing methods concurrently. These methodologies use filtering effects which gates that have bigger noise margin than glitch width eliminates glitch. In addition, we do limited optimization in boundary of node's slack. Therefore, the operated node's changes are for nothing in other node's slack.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.1-4
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• 2016

In this paper, we present an algorithm for adjusting the position of a user-specified object considering image aesthetics. Specifically, the user-specified object is positioned according to the rule of thirds by inserting or deleting unimportant seam lines from the image. To find such seam lines, a novel weight map is designed using the spatial and color distances from the object. We also design and analyze two approaches to seam carving and insertion. Experimental results show that the proposed method can be used as an effective semi-automatic image recomposition scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.49-54
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• 2010

This paper describes a fast circuit simulation technique using the latency insertion method (LIM) with a parallel and distributed leapfrog algorithm. The numerical simulation results on the PC cluster system that uses the cloud computing system are shown. As a result, it is confirmed that our method is very useful and practical.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.108-115
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• 2006

This paper presents a watermarking algorithm in the discrete wavelet transform domain using evolutionary algorithm. The proposed algorithm consists of wavelet-domain watermark insertion and genetic algorithm-based watermark extraction. More specifically watermark is inserted to the low-frequency region of wavelet transform domain, and watermark extraction is efficiently performed by using the evolutionary algorithm. The proposed watermarking algorithm is robust against various attacks such as JPEG and JPEG2000 image compression and geometric transformations.

• Journal of the Korean Society of Radiology
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• v.16 no.2
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• pp.131-139
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• 2022

The purpose of this study was to insert a pedicle screw into a pig thoracic vertebrae, a general CT scan(Non MAR), and a thoracic axial image obtained with the Metallic Artifact Reduction for Orthopedic Implants (O-MAR) to reduce artifacts. The image obtained by reconstructing the algorithm (Standard, Soft, Bone, Detail) was used using the image J program. Signal to noise ratio(SNR) and contrast to noise ratio(CNR) were compared and analyzed by obtaining measured values based on the given equation. And this study was to investigate tube voltage and algorithm suitable for CT scan for thoracic pedicle screw insertion. As a result, when non-MAR was used, the soft algorithm showed the highest SNR and CNR at 80, 100, 120, and 140 kVp, On the other hand, when MAR was used, the standard algorithm showed the highest at 80 kVp, and the standard and soft algorithms showed similar values at 100 kVp. At 120 kVp, the Soft and Standard algorithms showed similar values, and at 140 kVp, the Soft algorithm showed the highest SNR and CNR. Therefore, when comparing Non-MAR and MAR, even if MAR was used, SNR and CNR did not increase in all algorithms according to the change in tube voltage. In conclusion, it is judged that it is advantageous to use the Soft algorithm at 80, 100, 120, and 140 kVp in Non MAR, the Standard algorithm at 80 and 100 kVp in MAR, and the Soft algorithm at 120 and 140 kVp. This study is expected to serve as an opportunity to further improve the quality of images by using selective tube voltage and algorithms as basic data to help evaluate images of pedicle screw CT scans in the future.

• Journal of the Korea Society of Computer and Information
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• v.28 no.12
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• pp.79-87
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• 2023

In this paper, we propose a novel genetic algorithm to reduce the overall span time by optimizing the skid insertion sequence in the shipyard subassembly process. We represented a solution by a permutation of a set of skid ids and applied genetic operators suitable for such a representation. In addition, we combined the genetic algorithm and the existing heuristic algorithm called UniDev which is properly modified to improve the search performance. In particular, the slow skid search part in UniDev was changed to a greedy algorithm. Through extensive large-scaled simulations, it was observed that the span time of our method was stably minimized compared to Multi-Start search and a genetic algorithm combined with UniDev.