• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.231-233
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• 2004

Queuing is waiting lines which play routing service when packet entered. Queuing is decide how and whom is going to provide priority service. This is kind of first in first out(FIFO) or weighted fair queuing(WFQ) method. In this study, UDP design using WFQ way to serve to provide service evenly and rapidly in network. Also in actuality internet, datagram analyzed by packet captured. Queuing services through the requesting port number, input, output, output queuing creation & delete, message request by internet control message protocol(ICMP). Queuing designed in control block module, input queues, input/output module composition. In conclusion, I have confirm queuing result of WFQ method by the datagram information analyzed.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.301-303
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• 2004

현재 ATM 망에서 다양한 형태의 스위치 구조가 제안 되었으며 스위치 구조는 크게blocking 과 nonblocking 스위치로 나눌 수 있다. nonblocking 스위치는 버퍼의 위치에 따라 input queuing, output queuing, shared buffer switch로 나뉘며 그 중에 입력 버퍼형은 하드웨어 구현이 쉬운 장점이 있으나 HOL블로킹으로 인하여 처리 효율이 낮다는 단점이 있다. 본 논문에서는 이러한 입력 버퍼형 ATM 교환기의 문제점을 해결하기 위하여 가상적인 입력버퍼와 MUX를 이용한 입력버퍼형 반얀 스위치 모델을 제안한다.

• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Proceedings of the IEEK Conference
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• summer
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• pp.269-273
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• 2004

This paper presents a comparative performance analysis of a network accelerator model based on M/M/l queuing system. It assumes the Poisson distribution as its input traffic load. The decoding delay is employed as a performance analysis measure. Simulation results based on the proposed model show only $15\%$ differences with respect to actual measurements on field traffic for BCM5820 accelerator device. The performance analysis model provides with reasonable hardware structure of network servers, and can be used to span design spaces statistically.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.3
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• pp.549-555
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• 2000

We propose an approximate algorithm to analyze the queuing system with n bursty and heterogeneous arrival processes. Each input process is modeled by Interrupted Bernoulli Process(IBP). We approximate N arrival processes by a single state variable and subsequently simplify the transition probability matrix of the Markov chain associated with these N arrival processes. Using this single state variable of arrival processes, we describe the state of the queuing system and analyze the system numerically with the reduced transition probability matrix. We compute the queue length distribution, the delay distribution, and the loss probability. Comparisons with simulation data show that the approximation algorithm has a good accuracy.

• Journal of KIBIM
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• v.11 no.3
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• pp.34-44
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• 2021

This study quantitatively analyzes the work performance of the structural safety diagnosis team that diagnoses pipe racks. To this end, a method for evaluating the performance of the structural safety diagnosis team using the queuing model was proposed. For verification, the case of applying the existing method and the method of introducing a 3D laser scanner for one site was used. The period, number of people, and initial investment cost of each project were collected through interviews with case project experts. As a result of analyzing the performance of the structural safety diagnosis team using the queuing model, it was possible to confirm the probability of delay in the work of each project and the amount of delayed work. Through this, the cost (standby cost) when the project was delayed was analyzed. Finally, economic analysis was conducted in consideration of the waiting cost, labor cost, and initial investment cost. The results of this study can be used to decide whether to introduce 3D laser scanners.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.6
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• pp.365-371
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• 2003

Input queued switch is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queued. The input queued switch, however, suffers the HOL-Blocking, which limits its throughput to 58%. To overcome HOL-Blocking problem, many input-queued switch controlled by a scheduling algorithm. Most scheduling algorithms are implemented based on a centralized scheduler which restrict the design of the switch architecture. In this paper, we propose a simple scheduler called Pipelined Round Robin (PRR) which is intrinsically distributed by each input port. We presents to show the effectiveness of the proposed scheduler.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.3
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• pp.225-231
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• 1992

In this paper, queuing networks with open chains are considerd to analyze the performance of packet switching networks. Networks are classified into backbone and local access networks. Networks for performance analysis are distributed to twelve regions and DNS is the backbone. Analysis was conducted using the real values from the input to existing networks and mathematical estimation values. As the result of analysis, the mean of end-to-and delay for each chain was presented. Except special regions, we found that there was a little difference between real values and mathematical estimation values. However, there could be a performance problem in total networks due to the increase of communication volumes in each region. So we proposed some solutions to this problem.

• ETRI Journal
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• v.40 no.3
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• pp.337-346
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• 2018

In this paper, we propose a grant-aware (GA) scheduling algorithm that can provide higher throughput and lower latency than a conventional dual round-robin matching (DRRM) method. In our proposed GA algorithm, when an output receives requests from different inputs, the output not only sends a grant to the selected input, but also sends a grant indicator to all the other inputs to share the grant information. This allows the inputs to skip the granted outputs in their input arbiters in the next iteration. Simulation results using OPNET show that the proposed algorithm provides a maximum 3% higher throughput with approximately 31% less queuing delay than DRRM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.261-267
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• 2001

This paper presents the architecture of multiple-queue manager for input-queued switch, which has arbitration latency, and the design of the chip. The proposed architecture of multiple-queue manager provides wire-speed routing with a pipelined buffer management, and the tolerance of requests and grants data transmission latency between the input queue manager and central arbiter using a new request control method, which is based on a high-speed shifter. The multiple-input-queue manager has been implemented in a field programmable gate array chip, which provides OC-48c port speed. It enhances the maximum throughput of the input queuing switch up to 98.6% with 128-cell shared input buffer in 16$\times$16 switch size.