• Title/Summary/Keyword: Input limiter

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Fault current limitation characteristics of the Bi-2212 bulk coil for distribution-class superconducting fault current limiters (배전급 초전도 한류기 개발을 위한 Bi-2212 초전도 한류소자의 사고전류 제한 특성)

  • Sim, Jung-Wook;Kim, Hye-Rim;Yim, Seong-Woo;Hyun, Ok-Bae;Lee, Hai-Gun;Park, Kwon-Bae;Kim, Ho-Min;Lee, Bang-Wook;Oh, Il-Sung;Breuer, Frank;Bock, Joachim
    • Proceedings of the KIEE Conference
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    • 2006.07b
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    • pp.639-640
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    • 2006
  • We investigated fault current limitation characteristics of the resistive superconducting fault current limiter(SFCL) which consisted of a Bi-2212 bulk coil and a shunt coil. The Bi-2212 bulk coil and the shunt coil were connected in parallel. The Bi-2212 bulk coil was placed inside the shunt coil to induce field-assisted quench. The fault test was conducted at an input voltage of 200 $V_{rms}$ and fault current of 12 $kA_{rms}$ and 25 $kA_{rms}$. The fault conditions were asymmetric and symmetric, and the fault period was 5 cycles. The test results show that the SFCL successfully limited the fault current of 12 $kA_{rms}$ and 25 $kA_{rms}$ to below $5.5{\sim}6.9kA_{peak}$ within $0.64{\sim}2.17$ msec after the fault occurred. Limitation was faster under symmetric fault test condition due to the larger change rate of current. We concluded that the speed of fault current limitation was determined by the speed of current rise rather than the amplitude of a short circuit current. These results show that the Bi-2212 bulk coil is suitable for distribution-class SFCLs.

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Digitally Controlled Single-inductor Multiple-output Synchronous DC-DC Boost Converter with Smooth Loop Handover Using 55 nm Process

  • Hayder, Abbas Syed;Park, Young-Jun;Kim, SangYun;Pu, Young-Gun;Yoo, Sang-Sun;Yang, Youngoo;Lee, Minjae;Hwang, Keum Choel;Lee, Kang-Yoon
    • Journal of Power Electronics
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    • v.17 no.3
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    • pp.821-834
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    • 2017
  • This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

Design of Autonomous Independent Power System for USN Sensor Node Using Power CT (Power CT를 이용한 USN 센서노드용 자율독립전원 시스템 설계)

  • Son, Won-Kuk;Jeong, Jae-Kee
    • The Journal of Korean Institute of Information Technology
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    • v.16 no.12
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    • pp.101-107
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    • 2018
  • In wireless sensor network technology, which has been applied to various fields, the power supply and the power management of sensors are the most important issues. For this reason, a new concept of power supply and power management device is required. In this paper, we developed an autonomous independent power supply system that supplies the stable power to a sensor node without an additional external input by applying the energy harvesting technology using the electromagnetic induction principle by utilizing the current flowing in the transmission line. The proposed autonomous independent power supply system consists of a power supply using Power CT and a power management system including a charging circuit. The power management device uses a voltage limiter circuit and a monitoring circuit of charging voltage and current to ensure the safety of charging of the battery. In order to verify the performance of the proposed system, we applied it to the SVL diagnostic system and confirmed that it operates stably.

Robustness Evaluation of GaN Low-Noise Amplifier in Ka-band (Ka-대역 GaN 저잡음 증폭기의 강건성 평가)

  • Lee, Dongju;An, Se-Hwan;Joo, Ji-Han;Kwon, Jun-Beom;Kim, Younghoon;Lee, Sanghun;Seo, Mihui;Kim, Sosu
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.6
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    • pp.149-154
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    • 2022
  • Due to high power capabilities and high linearity of GaN devices, GaN Low-Noise Amplifiers (LNAs) without a limiter can be implemented in order to improve noise figure and reduce chip area in radar receivers. In this paper, a GaN LNA is presented for Ka-band radar receivers. The designed LNA was realized in a 150-nm GaN HEMT process and measurement results show that the voltage gain of >23 dB and the noise figure of <6.5 dB including packaging loss in the target frequency range. Under the high-power stress test, measured gain and noise figure of the GaN LNA is degraded after the first stress test, but no more degradation is observed under multiple stress tests. Through post-stress noise and s-parameter measurements, we verified that the GaN LNA is resilient to pulsed input power of ~40 dBm.