• Journal of Information Technology Services
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• 제7권3호
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• pp.271-286
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• 2008

The core of the semantic web is ontology, which supports interoperability among semantic web applications and enables developer to reuse and share domain knowledge. It used a variety of fields such as Information Retrieval, E-commerce, Software Engineering, Artificial Intelligence and Bio-informatics. However, the reality is that various errors might be included in conceptual hierarchy when developing ontologies. Therefore, methodologies and supporting tools are essential to help the developer construct suitable ontologies for the given purposes and to detect and analyze errors in order to verify the inconsistency in the ontologies. In this paper we propose a new approach for ontology error detection based on the Concept Lattices of Formal Concept Analysis. By using the tool that we developed in this research, we can extract core elements from the source code of Ontology and then detect some structural errors based on the concept lattices. The results of this research can be helpful for ontology engineers to support error detection and construction of "well-defined" and "good" ontologies.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제28권2C호
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• pp.201-208
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• 2003

The error concealment is very useful technique for real-time communication, such as video conference. In this paper. we propose the error concealment technique to minimize discontinuity of block boundary in consideration of the fact that human visual system is sensitive to discontinuity. The error concealment for each loss block is performed by extended block matching method based on gradient difference. In the simulation result, performance improvement for the proposed technique is on the average 1.32㏈ in comparison with the conventional technique.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2000년도 봄 학술발표논문집 Vol.27 No.1 (A)
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• pp.454-456
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• 2000

실시간의 특성을 가지는 데이터의 경우 네트워크상에서 분실된 패킷을 복구시키기 위해서 FEC 방법을 사용한다. FEC는 최소한의 지연만으로 손실 패킷의 복구를 효율적으로 할 수 있는 장점을 가지고 있으나 네트워크상에서의 패킷 손실 특성에 많이 의존되는 경향이 있다. ITU-T의 Study Group 16 에서의 Real-Time Transport Protocol(RTP)를 사용하여 네트워크에서 분실된 패킷을 복원시키는 방법으로 Media-independent error-correction scheme을 정하였다. 이 Scheme에 의해 만들어진 error-correction을 위한 신호화 media bitstream은 UDP 에 의해 encapsulation될 RTP에 실리게 된다. Scheme은 real-time이라는 환경에 유리하도록 bandwidth 와 latency 그리고 cost를 최소화하려고 했으며 이에 따라 네 가지 scheme을 정하였다. 네 가지의 Scheme은 오버헤드와 지연시간이 크기가 차별화를 두어 네트워크 환경의 변화에 적응하도록 하였다. 그러나 네트워크 환경에 보다 더 탄력적이며 효율적으로 적응하기 위해서 또 하나의 scheme을 제안한다. 새로 고안한 이 다섯 번째 scheme은 scheme 3 에 비해 작은 latency를 가지고 장점이 있는 반면 연속적으로 분실된 패킷에 대한 복원확률이 다소 떨어진다. 하지만 scheme 1과 2에 비해서는 연속적인 패킷 분실의 복원확률이 높아 네트워크환경에 따라 scheme 4를 사용하면 네 개의 scheme을 사용하여 분실패킷의 복원을 하는 경우보다 보다 효율적인 전송과 복원이 이루어질 것이다.

• Journal of Korea Society of Digital Industry and Information Management
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• 제7권2호
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• pp.1-8
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• 2011

In this study, software products developed in the course of testing, software managers in the process of testing software test and test tools for effective learning effects perspective has been studied using the NHPP software. The finite failure non-homogeneous Poisson process models presented and the life distribution applied extreme distribution which used to find the minimum (or the maximum) of a number of samples of various distributions. Software error detection techniques known in advance, but influencing factors for considering the errors found automatically and learning factors, by prior experience, to find precisely the error factor setting up the testing manager are presented comparing the problem. As a result, the learning factor is greater than automatic error that is generally efficient model could be confirmed. This paper, a numerical example of applying using time between failures and parameter estimation using maximum likelihood estimation method, after the efficiency of the data through trend analysis model selection were efficient using the mean square error.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권8호
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• pp.3749-3768
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• 2018

As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

• Journal of Korea Society of Industrial Information Systems
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• 제20권5호
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• pp.13-23
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• 2015

This thesis proposes a method for effectively detecting memory errors with low occurrence frequency that may occur depending on runtime situation by analyzing assembly codes obtained by disassembling an executable file. When applying the proposed method to various programs having no compilation error, a total of about 750 potential errors taken about 90 seconds are detected among 1 million lines of assembly codes corresponding to a total of about 10 thousand functions.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제14권1호
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• pp.65-74
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• 1989

This paperr presetns the Direct Decoding Method for binary BCH codes which can find the error locattion number directly from the syndrome without calculating the error locator polynomical. Also in this paper, the triple and quadruple error correcting BCH decoder are designed using this method. As an example, the triple error correcting (63.45) BCH decoder is implemented with TTL ICs. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제28권11C호
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• pp.1130-1139
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• 2003

In this work, we propose a multi-hypothesis error concealment algorithm, which replaces a lost block with a weighted superposition of more than two reference blocks in previous frames. Three methods are developed to find the set of reference blocks and determine the weighting coefficients. These methods are implemented based on H.26L standard, and their performances are evaluated. It is shown that the proposed multi-hypothesis algorithm provides up to 1.5㏈ better PSNR performance than the conventional single-hypothesis concealment algorithm.

• Transactions of the Korean Society of Mechanical Engineers A
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• 제25권9호
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• pp.1317-1324
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• 2001

In this paper, a methodology of geometrical error identification and compensation for NC machine tool position is developed. We propose a reference artifact with measuring the geometry of coordinate system for compensating linear scale error of NC machine. The coordinate system of the NC machine could be compensated successfully with the information obtained by measuring the reference artifact and our compensation algorithm. Monte Carlo simulation is used to evaluate coordinate referencing ability and, the uncertainties of the machine tool position is estimated and observed through the compensation process by simulation.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.