• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2609-2612
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• 2003

This paper describes a 64 channel signal generator/analyzer module that is useful for verification and testing of digital circuits. It can perform logic analyzer function and signal generator function at the same time. The 64 Channel module is implemented with single FPGA chip for miniaturization, and an USB interface is used to increase portability of the module. Multiple modules can be used in parallel for the verification of large scale circuits. Moreover, since the module is implemented as a PC based system, one can configure convenient GUI(Graphic User Interface) environment.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.11a
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• pp.297-300
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• 2003

This paper considers formal verification methods for enhancing software reliability. The formal method verifies that a software is correctly implemented according to its specification by using a mathematical formalism. This paper presents a partial survey on the formal methods and discusses possible applications for the improved software implementation. Finally, some topics are remarked as further studies.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.416-420
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• 1999

This paper describes a 32-bit RISC processor, which has instruction level compatibility with the ARM7 microprocessor. The processor is fully synthesizable, and its performance is evaluated based on 0.35-${\mu}{\textrm}{m}$ CMOS library. This paper focuses on the implementation of the processor and the reliable verification strategy ensuring the complete instruction level compatibility. The processor has successfully verified using a FPGA chip.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.799-800
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• 2006

This thesis implemented security systems of voice awareness which is higher accessible than existing security system using biological authentication system and is inexpensive in module of security device, and has an advantage in usability. Proposed the security systems of voice awareness implemented algorithm for characteristic extraction of inputted speaker's voice signal verification, and also implemented database of access control that is founded on extractible output. And a security system of voice awareness has a function of an authority of access control to system.

• Proceedings of the KSR Conference
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• 2000.05a
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• pp.292-299
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• 2000

An OBCS(on-board control system) which controls an operation of high speed train is a distributed control system which centrally supervises and controls a distributed system if independent units. A complicated process of design, implementation and test is needed to develop this system. The OBCS and its control algorithm are designed and verified by using the CASE Tool before it is implemented. Its functions are verified by the OBCS simulator. Hereafter, this verification process for Korean high-speed train being developed is presented.

• Speech Sciences
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• v.10 no.2
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• pp.65-75
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• 2003

This paper describes the issues associated with the real-time implementation of G.723.1A dual-rate speech coder on a TMS320VC5402 DSP. Firstly, the main features of the G.723.1A speech coder and the procedure involved in the implementation using assembly and C languages are discussed. Various real-time implementation issues such as memory/MIPS tradeoffs are also presented. For fixed-point implementation, we converted the ITU-T fixed-point ANSI C code into TMS320VC5402 code in the bit-exact way through verification using the test vectors. Finally, as the result of implementation, we present the MIPS and memory requirement for the real-time operation.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.251-257
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• 2010

The realization of u-City is coming near in some local governments by applying various city services, namely, u-City services to the city construction field to improve competitiveness of the city. But it is a reality that some local governments are experiencing many trial and errors in application of the u-City service in addition to the problem posing that the u-City service is not considering characteristics of development or application environment of an individual city. The present research proposes a service model for on-site application of the u-City service to solve this problem. The proposed model suggests a method for specifically conceptualizing and objectifying the on-site application that the existing concept-oriented model or an architecture-oriented model, etc. didn't provide. The verification system on effectiveness or effects of the u-City service model to remove ambiguity on the u-City service especially. The verification system of the u-City service model grasps the technology, function, procedure and target, etc. that the u-City service contains, evaluates whether the model satisfies conditions that the model should have, and secures objectivity and predictability of the u-City service model through confirmation on propriety, implementation and effectiveness, etc.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.23-36
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• 2018

Discrete Event System Specification (DEVS) has been used for decades as it provides sound semantics for hierarchical modular specification of discrete event systems. Instead of the mathematical specification, the DEVS diagram, based on the structured DEVS formalism, has provided more intuitive and convenient representation of complex DEVS models. This paper proposes a clean room process for implementation and verification of a DEVS diagram model specification into a simulation software source code. Specifically, it underlies a sequence of transformation steps from conformance and integrity checking of a given diagram model, translation into a corresponding tabular model, and finally conversion to a simulation source code, with each step being inversely verifiable for traceability. A simple example helps developers to understand the proposed process with associated transformation methods; a case study shows that the proposed process is effective for and adaptable to practical simulation software development.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.162-172
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• 2008

In this paper, we propose a multimodal speaker verification method using teeth image and voice as biometric trait for personal verification in mobile terminal equipment. The proposed method obtains the biometric traits using image and sound input devices of smart-phone that is one of mobile terminal equipments, and performs verification with biometric traits. In addition, the proposed method consists the multimodal-fashion of combining two biometric authentication scores for totally performance enhancement, the fusion method is accompanied a weighted-summation method which has comparative simple structure and superior performance for considering limited resources of system. The performance evaluation of proposed multimodal speaker authentication system conducts using a database acquired in smart-phone for 40 subjects. The experimental result shows 8.59% of EER in case of teeth verification 11.73% in case of voice verification and the multimodal speaker authentication result presented the 4.05% of EER. In the experimental result, we obtain the enhanced performance more than each using teeth and voice by using the simple weight-summation method in the multimodal speaker verification system.