• Journal of Electrical Engineering and Technology
• /
• v.8 no.2
• /
• pp.354-358
• /
• 2013

This paper discusses the analysis of arc conductance in a gas circuit breaker (GCB) during current interruption process and the investigation method of the interruption capability. There are some limitations in the application of the computational fluid dynamics (CFD) for the implementation of an arc model around the current zero, despite the fact that it gives good results for the high-current phase arc. In this study, we improved the accuracy in the analysis of the interruption performance by attempting the method using CFD and a mathematical arc model. The arc conductance at 200 ns before current zero (G-200ns) is selected as the indicator to predict the current interruption of the Short Line Fault (SLF). Finally, the proposed method is verified by applying to the actual circuit breakers which have different interruption performances.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.2
• /
• pp.800-811
• /
• 2018

This paper presents a regenerative braking control scheme for Switched Reluctance Machine (SRM) drive in Electric Vehicles (EVs). The main purpose is to maximize the recovered energy during battery charging by taking into account the nonlinear physical characteristics of the Switched Reluctance Machine. The proposed regenerative braking method employs the back-EMF in the generation process as a complicated position-dependent voltage source. The proposed maximum power recovery (MPR) operation of the regenerative braking is first based on the maximization of the extracted power from the machine and then the maximization of the power transferred to the battery. The maximum power extraction (MPE) from SRM is based on maximizing the energy conversion ratio by the calculation of the optimum PWM switching duty cycle, turn-on, and turn-off angles. By using the impedance matching theorem that allows the maximum power transfer (MPT) of the MPE, the proposed MPR is achieved. The parametric averaged value modeling of the machine phase currents in the chopping control mode is used for MPR realization. By following this model, a nonlinear equivalent input resistance is derived for the battery internal resistance matching. The effectiveness of the proposed regenerative braking method is demonstrated through simulation results and experimental implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.259-261
• /
• 2016

Cable is very essential material for ship operation as connecting element for whole electrical facilities of ship. The material cost and installation man-hour increment caused by re-installation is unavoidable if cable route has some problem. The purpose of this study is to suggest methods to implement the cable visualization functionality for verifying whether cable route is accurate or not in design phase. This functionality is conducted by representing color of 3D model for strong visibility by refer to textual cable routing information. The electrical engineer can provide cable route information more accurate and on time for cable installation department. As a result, the material cost and installation man-hour reduce due to decreasing ratio of re-installation.

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.8-10
• /
• 2005

In a general purpose inverter, a dead-time compensation strategy is very important for reducing torque ripples and acoustic noises of motors. However, in the case of small capacity inverter, the accurate dead-time compensation is hard to be obtained because a removal of the switching noise in a feedback current signal is difficult on condition of low-cost implementation. In this paper, the operation characteristics of the general purpose inverter applied the dead time compensation algorithm using an instantaneous back calculation of the phase angle of the current are presented.

• Journal of Power Electronics
• /
• v.16 no.3
• /
• pp.849-860
• /
• 2016

The high-switching-frequency operation of power converters can achieve high power density through size reduction of passive components, such as capacitors, inductors, and transformers. However, a small-output capacitor that has small capacitance and low effective series resistance changes the small-signal model of the converter power stage. Such a capacitor can make the converter unstable by increasing the crossover frequency in the transfer function of the small-signal model. In this paper, the design and implementation of a high-frequency LLC resonant converter are presented to verify the power density enhancement achieved by decreasing the size of passive components. The effect of small output capacitance is analyzed for stability by using a proper small-signal model of the LLC resonant converter. Finally, proper design methods of a feedback compensator are proposed to obtain a sufficient phase margin in the Bode plot of the loop gain of the converter for stable operation at 500 kHz switching frequency. A theoretical approach using MATLAB, a simulation approach using PSIM, and experimental results are presented to show the validity of the proposed analysis and design methods with 100 and 500 kHz prototype converters.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.20 no.5
• /
• pp.437-447
• /
• 2015

In this paper, implementation of an integrated transformer applicable to power supply units (PSUs) for a 150-W LED with a wide range of output voltage is presented. The transformer is comprised of a PFC inductor and an LLC resonant transformer, each of which is placed and integrated on an E-I-E-type magnetic core. Integrated transformers with two different air gap topologies (i.e., the side and center gap topologies) are considered in the design phase to investigate their applicability. The design consideration on the LLC resonant converter used for the wide-output-voltage control ranges is described, and the overall performance of the proposed system is verified through realization of it onto a 150-W LED PSU board.

• Journal of Power Electronics
• /
• v.13 no.1
• /
• pp.59-69
• /
• 2013

An alternative technique to control multilevel inverters with vector approximations has been presented. The innovative control method utilizes specially designed two-dimensional hysteresis comparators to simplify the implementation and improve the resultant waveform. The multistage inverter designed with maximum number of levels is operated in such a way to approximate the reference voltage vector by exploiting the large number of multilevel inverter vectors. A three-stage inverter with the main high voltage stage made of three phase, six-switch and singly-fed inverter is considered for application to the proposed design. The proposed control concept is to maintain a higher voltage stage state as long as it can lead to a target vector. High and medium voltage stages controllers are based on surface hysteresis comparators to hold the switching state or to perform the necessary change to achieve its reference voltage with minimal switching losses. The low voltage stage controller is designed to approximate the target reference voltage to the nearest inverter vector using the nearest integer rounding and adjustment comparators. Model simulation and prototype test results show that the proposed control technique clearly outperforms the previous control methods.

• Journal of Power Electronics
• /
• v.13 no.1
• /
• pp.20-30
• /
• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.35 no.1
• /
• pp.26-35
• /
• 1986

In this paper, non-linear state equations for a 3-phase, 220V, 0.4 KW, squirrel cage induction motor have been derived using the d-q transformation and then these equations have been linearized around an operating point by a small perturbation method. Root loci on the s-plane with repect to the changes of slip S and supply frequency f have been studied. Based on the above results, the derived linear state equations have been augmented to the 6th order, including the output velocity feedback and a discrete PI speed controller. Using the new state equations, stability regions on the Kp-Kl plane have been investigated for slip S and sampling time T. In designing a discrete PI controller, the coefficients Kp and Kl around the normal operating point (220V,1,692rpm,60Hz)have been chosen under the assumptions that each response to a perturbation input of reference speed and load torque be underdamped and dominated by a pair of complex poles. Step responses in the experimental system using an Intel SDK-86 and an optimized PWM inverter show satisfactory results that the maximum overshoots and damped frequency are well coincided with ones from the computer simulation.

• ETRI Journal
• /
• v.37 no.3
• /
• pp.584-594
• /
• 2015

To date, many different kinds of logic styles for hardware countermeasures have been developed; for example, SABL, TDPL, and DyCML. Current mode-based logic styles are useful as they consume less power compared to voltage mode-based logic styles such as SABL and TDPL. Although we developed TPDyCML in 2012 and presented it at the WISA 2012 conference, we have further optimized it in this paper using a binary decision diagram algorithm and confirmed its properties through a practical implementation of the AES S-box. In this paper, we will explain the outcome of HSPICE simulations, which included correlation power attacks, on AES S-boxes configured using a compact NMOS tree constructed from either SABL, CMOS, TDPL, DyCML, or TPDyCML. In addition, to compare the performance of each logic style in greater detail, we will carry out a mutual information analysis (MIA). Our results confirm that our logic style has good properties as a hardware countermeasure and 15% less information leakage than those secure logic styles used in our MIA.