• Title/Summary/Keyword: Image chip

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TILT CORRECTION FOR A WIDE-FIELD ON-AXIS TELESCOPE USING THE SYMMETRICITY OF OPTICAL ABERRATIONS

  • Lee, Chung-Uk;Kim, Yunjong;Kim, Seung-Lee;Lee, Dong-Joo;Cha, Sang-Mok;Lee, Yongseok;Kim, Dong-Jin
    • Journal of The Korean Astronomical Society
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    • v.54 no.4
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    • pp.113-119
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    • 2021
  • It is difficult for observers to conduct an optical alignment at an observatory without the assistance of an optical engineer if optomechanical parts are to be replaced at night. We present a practical tilt correction method to obtain the optimal optical alignment condition using the symmetricity of optical aberrations of a wide-field on-axis telescope at night. We conducted coarse tilt correction by visually examining the symmetry of two representative star shapes obtained at two guide chips facing each other, such as east-west or north-south pairs. After coarse correction, we observed four sets of small stamp images using four guide cameras located at each cardinal position by changing the focus positions in 10-㎛ increments and passing through the optimum focus position in the range of ±200 ㎛. The standard deviation of each image, as a function of the focus position, was fitted with a second-order polynomial function to derive the optimal focus position at each cardinal edge. We derived the tilt angles from the slopes converted by the distance and the focus position difference between two paired guide chip combinations such as east-west and north-south. We used this method to collimate the on-axis wide-field telescope KMTNet in Chile after replacing two old focus actuators. The total optical alignment time was less than 30 min. Our method is practical and straightforward for maintaining the optical performance of wide-field telescopes such as KMTNet.

Smart Radar System for Life Pattern Recognition (생활패턴 인지가 가능한 스마트 레이더 시스템)

  • Sang-Joong Jung
    • Journal of the Institute of Convergence Signal Processing
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    • v.23 no.2
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    • pp.91-96
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    • 2022
  • At the current camera-based technology level, sensor-based basic life pattern recognition technology has to suffer inconvenience to obtain accurate data, and commercial band products are difficult to collect accurate data, and cannot take into account the motive, cause, and psychological effect of behavior. the current situation. In this paper, radar technology for life pattern recognition is a technology that measures the distance, speed, and angle with an object by transmitting a waveform designed to detect nearby people or objects in daily life and processing the reflected received signal. It was designed to supplement issues such as privacy protection in the existing image-based service by applying it. For the implementation of the proposed system, based on TI IWR1642 chip, RF chipset control for 60GHz band millimeter wave FMCW transmission/reception, module development for distance/speed/angle detection, and technology including signal processing software were implemented. It is expected that analysis of individual life patterns will be possible by calculating self-management and behavior sequences by extracting personalized life patterns through quantitative analysis of life patterns as meta-analysis of living information in security and safe guards application.

Development of an FPGA-based Sealer Coating Inspection Vision System for Automotive Glass Assembly Automation Equipment (자동차 글라스 조립 자동화설비를 위한 FPGA기반 실러 도포검사 비전시스템 개발)

  • Ju-Young Kim;Jae-Ryul Park
    • Journal of Sensor Science and Technology
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    • v.32 no.5
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    • pp.320-327
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    • 2023
  • In this study, an FPGA-based sealer inspection system was developed to inspect the sealer applied to install vehicle glass on a car body. The sealer is a liquid or paste-like material that promotes adhesion such as sealing and waterproofing for mounting and assembling vehicle parts to a car body. The system installed in the existing vehicle design parts line does not detect the sealer in the glass rotation section and takes a long time to process. This study developed a line laser camera sensor and an FPGA vision signal processing module to solve this problem. The line laser camera sensor was developed such that the resolution and speed of the camera for data acquisition could be modified according to the irradiation angle of the laser. Furthermore, it was developed considering the mountability of the entire system to prevent interference with the sealer ejection machine. In addition, a vision signal processing module was developed using the Zynq-7020 FPGA chip to improve the processing speed of the algorithm that converted the profile to the sealer shape image acquired from a 2D camera and calculated the width and height of the sealer using the converted profile. The performance of the developed sealer application inspection system was verified by establishing an experimental environment identical to that of an actual automobile production line. The experimental results confirmed the performance of the sealer application inspection at a level that satisfied the requirements of automotive field standards.

Integrated Rotary Genetic Analysis Microsystem for Influenza A Virus Detection

  • Jung, Jae Hwan;Park, Byung Hyun;Choi, Seok Jin;Seo, Tae Seok
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.88-89
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    • 2013
  • A variety of influenza A viruses from animal hosts are continuously prevalent throughout the world which cause human epidemics resulting millions of human infections and enormous industrial and economic damages. Thus, early diagnosis of such pathogen is of paramount importance for biomedical examination and public healthcare screening. To approach this issue, here we propose a fully integrated Rotary genetic analysis system, called Rotary Genetic Analyzer, for on-site detection of influenza A viruses with high speed. The Rotary Genetic Analyzer is made up of four parts including a disposable microchip, a servo motor for precise and high rate spinning of the chip, thermal blocks for temperature control, and a miniaturized optical fluorescence detector as shown Fig. 1. A thermal block made from duralumin is integrated with a film heater at the bottom and a resistance temperature detector (RTD) in the middle. For the efficient performance of RT-PCR, three thermal blocks are placed on the Rotary stage and the temperature of each block is corresponded to the thermal cycling, namely $95^{\circ}C$ (denature), $58^{\circ}C$ (annealing), and $72^{\circ}C$ (extension). Rotary RT-PCR was performed to amplify the target gene which was monitored by an optical fluorescent detector above the extension block. A disposable microdevice (10 cm diameter) consists of a solid-phase extraction based sample pretreatment unit, bead chamber, and 4 ${\mu}L$ of the PCR chamber as shown Fig. 2. The microchip is fabricated using a patterned polycarbonate (PC) sheet with 1 mm thickness and a PC film with 130 ${\mu}m$ thickness, which layers are thermally bonded at $138^{\circ}C$ using acetone vapour. Silicatreated microglass beads with 150~212 ${\mu}L$ diameter are introduced into the sample pretreatment chambers and held in place by weir structure for construction of solid-phase extraction system. Fig. 3 shows strobed images of sequential loading of three samples. Three samples were loaded into the reservoir simultaneously (Fig. 3A), then the influenza A H3N2 viral RNA sample was loaded at 5000 RPM for 10 sec (Fig. 3B). Washing buffer was followed at 5000 RPM for 5 min (Fig. 3C), and angular frequency was decreased to 100 RPM for siphon priming of PCR cocktail to the channel as shown in Figure 3D. Finally the PCR cocktail was loaded to the bead chamber at 2000 RPM for 10 sec, and then RPM was increased up to 5000 RPM for 1 min to obtain the as much as PCR cocktail containing the RNA template (Fig. 3E). In this system, the wastes from RNA samples and washing buffer were transported to the waste chamber, which is fully filled to the chamber with precise optimization. Then, the PCR cocktail was able to transport to the PCR chamber. Fig. 3F shows the final image of the sample pretreatment. PCR cocktail containing RNA template is successfully isolated from waste. To detect the influenza A H3N2 virus, the purified RNA with PCR cocktail in the PCR chamber was amplified by using performed the RNA capture on the proposed microdevice. The fluorescence images were described in Figure 4A at the 0, 40 cycles. The fluorescence signal (40 cycle) was drastically increased confirming the influenza A H3N2 virus. The real-time profiles were successfully obtained using the optical fluorescence detector as shown in Figure 4B. The Rotary PCR and off-chip PCR were compared with same amount of influenza A H3N2 virus. The Ct value of Rotary PCR was smaller than the off-chip PCR without contamination. The whole process of the sample pretreatment and RT-PCR could be accomplished in 30 min on the fully integrated Rotary Genetic Analyzer system. We have demonstrated a fully integrated and portable Rotary Genetic Analyzer for detection of the gene expression of influenza A virus, which has 'Sample-in-answer-out' capability including sample pretreatment, rotary amplification, and optical detection. Target gene amplification was real-time monitored using the integrated Rotary Genetic Analyzer system.

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Analysis of Optimal Resolution and Number of GCP Chips for Precision Sensor Modeling Efficiency in Satellite Images (농림위성영상 정밀센서모델링 효율성 재고를 위한 최적의 해상도 및 지상기준점 칩 개수 분석)

  • Choi, Hyeon-Gyeong;Kim, Taejung
    • Korean Journal of Remote Sensing
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    • v.38 no.6_1
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    • pp.1445-1462
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    • 2022
  • Compact Advanced Satellite 500-4 (CAS500-4), which is scheduled to be launched in 2025, is a mid-resolution satellite with a 5 m resolution developed for wide-area agriculture and forest observation. To utilize satellite images, it is important to establish a precision sensor model and establish accurate geometric information. Previous research reported that a precision sensor model could be automatically established through the process of matching ground control point (GCP) chips and satellite images. Therefore, to improve the geometric accuracy of satellite images, it is necessary to improve the GCP chip matching performance. This paper proposes an improved GCP chip matching scheme for improved precision sensor modeling of mid-resolution satellite images. When using high-resolution GCP chips for matching against mid-resolution satellite images, there are two major issues: handling the resolution difference between GCP chips and satellite images and finding the optimal quantity of GCP chips. To solve these issues, this study compared and analyzed chip matching performances according to various satellite image upsampling factors and various number of chips. RapidEye images with a resolution of 5m were used as mid-resolution satellite images. GCP chips were prepared from aerial orthographic images with a resolution of 0.25 m and satellite orthogonal images with a resolution of 0.5 m. Accuracy analysis was performed using manually extracted reference points. Experiment results show that upsampling factor of two and three significantly improved sensor model accuracy. They also show that the accuracy was maintained with reduced number of GCP chips of around 100. The results of the study confirmed the possibility of applying high-resolution GCP chips for automated precision sensor modeling of mid-resolution satellite images with improved accuracy. It is expected that the results of this study can be used to establish a precise sensor model for CAS500-4.

Design of a Bit-Serial Divider in GF(2$^{m}$ ) for Elliptic Curve Cryptosystem (타원곡선 암호시스템을 위한 GF(2$^{m}$ )상의 비트-시리얼 나눗셈기 설계)

  • 김창훈;홍춘표;김남식;권순학
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.12C
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    • pp.1288-1298
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    • 2002
  • To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.

Compression and Performance Evaluation of CNN Models on Embedded Board (임베디드 보드에서의 CNN 모델 압축 및 성능 검증)

  • Moon, Hyeon-Cheol;Lee, Ho-Young;Kim, Jae-Gon
    • Journal of Broadcast Engineering
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    • v.25 no.2
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    • pp.200-207
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    • 2020
  • Recently, deep neural networks such as CNN are showing excellent performance in various fields such as image classification, object recognition, visual quality enhancement, etc. However, as the model size and computational complexity of deep learning models for most applications increases, it is hard to apply neural networks to IoT and mobile environments. Therefore, neural network compression algorithms for reducing the model size while keeping the performance have been being studied. In this paper, we apply few compression methods to CNN models and evaluate their performances in the embedded environment. For evaluate the performance, the classification performance and inference time of the original CNN models and the compressed CNN models on the image inputted by the camera are evaluated in the embedded board equipped with QCS605, which is a customized AI chip. In this paper, a few CNN models of MobileNetV2, ResNet50, and VGG-16 are compressed by applying the methods of pruning and matrix decomposition. The experimental results show that the compressed models give not only the model size reduction of 1.3~11.2 times at a classification performance loss of less than 2% compared to the original model, but also the inference time reduction of 1.2~2.21 times, and the memory reduction of 1.2~3.8 times in the embedded board.

An Algorithm for Spot Addressing in Microarray using Regular Grid Structure Searching (균일 격자 구조 탐색을 이용한 마이크로어레이 반점 주소 결정 알고리즘)

  • 진희정;조환규
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.9
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    • pp.514-526
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    • 2004
  • Microarray is a new technique for gene expression experiment, which has gained biologist's attention for recent years. This technology enables us to obtain hundreds and thousands of expression of gene or genotype at once using microarray Since it requires manual work to analyze patterns of gene expression, we want to develop an effective and automated tools to analyze microarray image. However it is difficult to analyze DNA chip images automatically due to several problems such as the variation of spot position, the irregularity of spot shape and size, and sample contamination. Especially, one of the most difficult problems in microarray analysis is the block and spot addressing, which is performed by manual or semi automated work in all the commercial tools. In this paper we propose a new algorithm to address the position of spot and block using a new concept of regular structure grid searching. In our algorithm, first we construct maximal I-regular sequences from the set of input points. Secondly we calculate the rotational angle and unit distance. Finally, we construct I-regularity graph by allowing pseudo points and then we compute the spot/block address using this graph. Experiment results showed that our algorithm is highly robust and reliable. Supplement information is available on http://jade.cs.pusan.ac.kr/~autogrid.

Automated Geometric Correction of Geostationary Weather Satellite Images (정지궤도 기상위성의 자동기하보정)

  • Kim, Hyun-Suk;Lee, Tae-Yoon;Hur, Dong-Seok;Rhee, Soo-Ahm;Kim, Tae-Jung
    • Korean Journal of Remote Sensing
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    • v.23 no.4
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    • pp.297-309
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    • 2007
  • The first Korean geostationary weather satellite, Communications, Oceanography and Meteorology Satellite (COMS) will be launched in 2008. The ground station for COMS needs to perform geometric correction to improve accuracy of satellite image data and to broadcast geometrically corrected images to users within 30 minutes after image acquisition. For such a requirement, we developed automated and fast geometric correction techniques. For this, we generated control points automatically by matching images against coastline data and by applying a robust estimation called RANSAC. We used GSHHS (Global Self-consistent Hierarchical High-resolution Shoreline) shoreline database to construct 211 landmark chips. We detected clouds within the images and applied matching to cloud-free sub images. When matching visible channels, we selected sub images located in day-time. We tested the algorithm with GOES-9 images. Control points were generated by matching channel 1 and channel 2 images of GOES against the 211 landmark chips. The RANSAC correctly removed outliers from being selected as control points. The accuracy of sensor models established using the automated control points were in the range of $1{\sim}2$ pixels. Geometric correction was performed and the performance was visually inspected by projecting coastline onto the geometrically corrected images. The total processing time for matching, RANSAC and geometric correction was around 4 minutes.

Fabrication Method of High-density and High-uniformity Solder Bump without Copper Cross-contamination in Si-LSI Laboratory (실리콘 실험실에 구리 오염을 방지 할 수 있는 고밀도/고균일의 Solder Bump 형성방법)

  • 김성진;주철원;박성수;백규하;이희태;송민규
    • Journal of the Microelectronics and Packaging Society
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    • v.7 no.4
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    • pp.23-29
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    • 2000
  • We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

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