• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.20-25
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• 2016

This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.691-697
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• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.6
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• pp.594-598
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• 2008

In this paper we propose a fast booting technique based on Improved snapshot boot in embedded Linux, widely adopted in personal devices such as PDA and mobile phones. The existing Snapshot boot technique tries to create a snapshot image at the time of suspend, and later load the entire snapshot image into the system memory at the predefined location with the help of a bootloader at the time of resume. Since a bootloader has to copy the entire snapshot image into the predefined memory to resume the previous suspended computing state, a little bit long time is required to resume. Improved snapshot boot does not create a snapshot image consisting of whole memory pages at the time of suspend, thus resulting in smaller snapshot image than the existing snapshot boot. The remaining pages are in the swap area. The resulting smaller sized snapshot image enables much faster booting latency. Through the experiment, we can see the booting latency is reduced almost 30% with suspend image of 2982 pages. This result depends on the amount of swap-out pages.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.157-169
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• 2013

Scale Invariant Feature Transform (SIFT) generates image features widely used to match objects in different images. Previous work on hardware-based SIFT implementation requires excessive internal memory and hardware logic [1]. In this paper, a new hardware organization is proposed to implement SIFT with less memory and hardware cost than the previous work. To this end, a parallel Gaussian filter bank is adopted to eliminate the buffers that store intermediate results because parallel operations allow all intermediate results available at the same time. Furthermore, the processing order is changed from the raster-scan order to the block-by-block order so that the line buffer size storing the source image is also reduced. These techniques trade the reduction of memory size with a slight increase of the execution time and external memory bandwidth. As a result, the memory size is reduced by 94.4%. The proposed hardware for SIFT implementation includes the Descriptor generation block, which is omitted in the previous work [1]. The addition of the hardwired descriptor generation improves the computation speed by about 30 times when compared with the previous work.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.8
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• pp.669-673
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• 2011

The charged particle type display is a kind of the reflectivity type display and shows an image by absorption and reflection of external light source, which has keep an image without additional electric power because of bistability. In this paper, we made a device whose cell gap is $56\;{\mu}m$ and also analyzed driving and memory characteristics by applied driving voltages. As a result, we found that the driving voltage and memory effect depend on q/m(charge to mass ratio) of charged particle. In this case of breakdown voltage, the devices showed degradation of reflectivity and memory effect due to irregular movement of overcharged particles. In addition, contrast ratio of the device varies with memory effect. Thus, we consider that device needs uniform q/m for improvement of electric and optical properties and memory effect.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• KIISE Transactions on Computing Practices
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• v.22 no.8
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• pp.363-368
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• 2016

A storage-based VDI (Virtual Desktop Infrastructure) system has the disadvantage of degraded performance when IOs for the VDI system are concentrated on the storage. The performance of the VDI system decreases rapidly especially, in case of the boot storm wherein all virtual desktops boot simultaneously. In this paper, we propose a main memory-based virtual desktop system managing virtual desktop images on main memory to solve the performance degradation problem including the boot storm. Performance of the main memory-based VDI system is improved by storing the virtual desktop image on the main memory. Also, the virtual desktop images with large size can be stored in the main memory using deduplication technology. Implementation of the proposed VDI system indicated that it has 4 times performance benefit than the storage-based VDI system in case of the boot storm.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.115-117
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• 2001

대부분의 embedded system에서 hard-disk 대용으로 flash memory를 사용하고 있으며, flash device에 압축 커널이미지와 root file system image를 가지고 있다. Booting 고정 중 커널의 압축이 풀리고 메모리에 로드되어 제어를 넘겨받으면 flash memory 상에 존재하는 root file system image를 ramdisk의 image로 로드하여 시스템은 결국 ramdisk에 root file system을 가지게 된다. Ramdisk 상의 프로그램을 실행하기 위해 메모리로 실행파일 이미지를 copy하는 과정을 피하고 ramdisk 상의 이미지를 바로 프로세스의 virtual memory area에 직접 매핑 시켜 주는 XIP(eXection-In-Place)를 구현함으로써 많은 메모리 절감 효과를 얻을 수 있다. 본 연구에서는 ramdisk를 root file system으로 사용하는 embedded system에서의 XIP 구조를 설계하고 구현하였다.

• Journal of the Korea Society of Computer and Information
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• v.23 no.1
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• pp.25-32
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• 2018

In this paper, we propose an edge detection algorithm for auto focus of infrared camera. We designed and implemented the edge detection of infrared image by using a spatial filter on FPGA. The infrared camera should be designed to minimize the image processing time and usage of hardware resource because these days surveillance systems should have the fast response and be low size, weight and power. we applied the $3{\times}3$ mask filter which has an advantage of minimizing the usage of memory and the propagation delay to process filtering. When we applied Laplacian filter to extract contour data from an image, not only edge components but also noise components of the image were extracted by the filter. These noise components make it difficult to determine the focus state. Also a bad pixel of infrared detector causes a problem in detecting the edge components. So we propose an adaptive edge detection filter that is a method to extract only edge components except noise components of an image by analyzing a variance of pixel data in $3{\times}3$ memory area. And we can detect the bad pixel and replace it with neighboring normal pixel value when we store a pixel in $3{\times}3$ memory area for filtering calculation. The experimental result proves that the proposed method is effective to implement the edge detection for auto focus in infrared camera.