• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5B
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• pp.285-295
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• 2008

Internet routers perform packet forwarding which determines a next hop for each incoming packet using the packet's destination IP address. IP address lookup becomes one of the major challenges because it should be performed in wire-speed for every incoming packet under the circumstance of the advancement in link technologies and the growth of the number of the Internet users. Many binary search algorithms have been proposed for fast IP address lookup. However, tree-based binary search algorithms are usually unbalanced, and they do not provide very good search performance. Even for binary search algorithms providing balanced search, they have drawbacks requiring prefix duplication. In this paper, a new binary search algorithm which provides the balanced binary search and the number of its entries is much less than the number of original prefixes. This is possible because of composing the binary search tree only with disjoint prefixes of the prefix set. Each node has a prefix vector that has the prefix nesting information. The number of memory accesses of the proposed algorithm becomes much less than that of prior binary search algorithms, and hence its performance for IP address lookup is considerably improved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1642-1651
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• 2004

Advance of internet access technology requires more internet bandwidth and high-speed packet processing. IP address lookups in routers are essential elements which should be performed in real time for packets arriving tens-of-million packets per second. In this paper, we proposed a new architecture for efficient IP address lookup. The proposed scheme produces multiple balanced trees stored into a single SRAM. The proposed scheme performs sequential binary searches on multiple trees. Performance evaluation results show that p개posed architecture requires 301.7KByte SRAM to store about 40,000 prefix samples, and an address lookup is achieved by 11.3 memory accesses in average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1B
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• pp.18-28
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• 2004

Efficient hardware implementation of address lookup is one of the most important design issues of internet routers. Address lookup significantly impacts router performance since routers need to process tens-to-hundred millions of packets per second in real time. In this paper, we propose a practical IP address lookup structure based on the binary tree of prefixes of different lengths. The proposed structure produces multiple balanced trees, and hence it solve the issues due to the unbalanced binary prefix tree of the existing scheme. The proposed structure is implemented using pipelined binary search combined with a small size TCAM. Performance evaluation results show that the proposed architecture requires a 2000-entry TCAM and total 245 kbyte SRAMs to store about 30,000 prefix samples from MAE-WEST router, and an address lookup is achieved by a single memory access. The proposed scheme scales very well with both of large databases and longer addresses as in IPv6.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.613-619
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• 2001

The IP address lookup problem is to find the longest matching IP prefix for a given IP address from the routing table and has been a central bottleneck in speeding up the Internet. In this paper, we propose a new algorithm for this problem based on the segment tree data structure. Given n IP prefixes, our algorithm can do IP address in Ο(log n) time. It also handles the insertion and deletion of IP prefixes efficiently without rebuilding the total data structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.43-50
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• 2001

The IP routing uses the longest-matching prefix to determine the destination. Fast lookup should be required for the high speed routing. We propose a modified LC-trie, called multiple LC-trie, which is suitable data structure for fast address-lookups in software implementation. To reduce the number of memory accesses, our scheme analyzes the distribution of IP address access pattern, and constructs multiple LC:-tries for frequently accessed IP addresses. Our experimental results show that our scheme can perform faster than the original LC-trie schemes.

• Journal of the Korea Society of Computer and Information
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• v.20 no.12
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• pp.45-52
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• 2015

We propose a hybrid prefix caching scheme to enable high speed IP address lookup. All prefixes loaded in a prefix cache should not be overlapped in address range for correct IP lookup. So, every non-leaf prefix needs to be expanded not so as to be overlapped. The shorter expanded prefix is more preferable because it can cover wider address range just as an single entry in a prefix cache. We exploits advantages of two dynamic prefix expansion techniques, bounded prefix expansion technique and bitmap-based prefix expansion technique. The proposed scheme uses dual bound values whereas just one bound value is used in bounded prefix expansion. Our elaborated technique make the dual bound values be associated with several subtries flexibly using bitmap information, rather than with fixed subtries. We evaluate the performance of the proposed scheme in terms of the average length of the expanded prefixes and cache miss ratio. The experiment results show the proposed scheme has lower cache miss ratio than other previous schemes including both bounded prefix expansion and bitmap-based expansion irrespective of the cache size.

• Journal of Korea Multimedia Society
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• v.9 no.2
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• pp.244-254
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• 2006

This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.137-146
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• 2006

IP address lookup has become a major bottleneck of packet forwarding and a critical issue for high-speed networking techniques in routers. In this paper, we propose an efficient high-speed IP address lookup scheme using adaptive multiple hashing and prefix grouping. According to our analysis results based on routing data distributions, we grouped prefix lengths and selected the number of hash functions in each group adaptively. As a result, we can reduce collisions caused by hashing. Accordingly, a forwarding table of our scheme has good memory efficiency, and thus is organized with the proper number of memory modules. Also, the proposed scheme has the fast building and searching mechanisms to develop the forwarding table only during a single memory access.