• Journal of the Korea Institute of Information and Communication Engineering
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• 제9권8호
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제11권2호
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• pp.95-100
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• 2011

This paper analyzes the interference effect of WLAN(Wireless Local Area Network) service on WiBro(Wireless Broadband) service in adjacent frequency band by using Monte Carlo method. For the analysis, we make scenario that WLAN service operates on frequency band of 2401 MHz ~ 2423 MHz and WiBro service operates on frequency band of 698 MHz ~ 704 MHz. In case of WiBro receiver is close to WLAN AP(Access Point), the interference will be increased. So, we calculate the protection distance between WiBro receiver and WLAN AP to meet interference probability of 5 % below and required interference power of WLAN AP to meet interference probability of 5 % below in the case of fixed protection distance. As a result, the protection distance of 60 m and -9.5 dBm of required interference power of WLAN AP at 10 m of the fixed protection distance are analyzed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제23권10호
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• pp.90-99
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• 2009

In this paper, we proposed the new class-E frequency multiplier design that include the highest efficient characteristics. The proposed frequency multiplier is designed for 5.8[GHz] output using the frequency multiplier about 2.9[GHz] input signal. And studying in this paper is for the design and the implementation of the class E frequency multiplier. For the result, the maximum highest efficient characteristics 32[%] which is with output power 24.5[dBm] and 8.5[dB], is shown with frequency multiplier for the 2.9/5.8[GHz] class E. And we applied the linear method to the implemented class E frequency multiplier. As a result, the output spectrum for the linear is upgrade to 12[dB], 12[dB], 13[dB] of the ACPR characteristics on the +11[MHz], +20[MHz], +30[MHz] offset frequency in the center frequency. The result is satisfied with the 3.83[%] of the lineared EVM for the 64-QAM modulated method with the 54[Mbps] transmission velocity. In this paper, we show that the good compensation result of the linearity and the efficiency through the digital pre-linear method of the distortion with the frequency multiplier. Therefore, we suggested the frequency multiplier method are applying to WLAN, cellular, PCS, WCDMA, and etc.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.820-824
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• 2004

Personal Robot System in developing, have a module architecture, each module are connected through heterogeneors network systems like Ethernet, WLAN (802.11), IEEE1394 (Firewire), Bluetooth, USB, CAN, or RS-232C. In developing personal robot system we think that the key of robot performance is interoperability among modules. Each network protocol are well connected in the view of network system for the interoperability. So we make a bridging architecture that can routing, converting, transporting data packets with matcing each network's properties. Furthermore we suggest a advanced design scheme for realtime / non-realtime and control signal (short, requiring hard-realtime) / multimedia data (large, requiring soft-realtime). By some application systems, we could test performance, interoperability and stability. In this paper, we show our design concept, middleware architecture, and some applications systems using this middleware.

• The Journal of Information Technology
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• 제6권3호
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• pp.65-73
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• 2003

The evaluation AP embedded Linux board is implemented. The board is made of IBM 405 GP processor, PPCBoot-1.2.1 boot loader, Linux-2.4.21 kernel and root file system. The evaluation board has two flash memories, boot flash and application flash of size 512Kbyte and 16Mbyte, respectively. And it supports IEEE 802.11a which provide the maximum throughput of 54Mbps in the 5.2GHz frequency band. MTD(Memory Technology Device) and JFFS2(Journalling Flash File System version 2) technologies are adopted to optimally package the system software, boot loader, kernel and root file system. And in order to optimize root file system, busybox package and tiny login are used. Linux kernel and root file system is combined together with mkimage utility.

• Journal of KIISE:Information Networking
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• 제37권4호
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• pp.307-311
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• 2010

Most wireless ad hoc networks use sender-centric carrier sensing where a data sender determines the transmission timing through channel assessment. However, sender-centric carrier sensing suffers from both exposed and hidden terminal problems even with physical and virtual carrier sensing. In this paper, we propose a new receiver-centric carrier sense (RCS) technique where a data receiver triggers packet transmission based on local channel assessment. Through both numerical analysis and simulation studies, we show that the proposed RCS achieves up to 20.9% higher throughput than previous receiver-centric approaches.

• Journal of Advanced Navigation Technology
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• 제13권5호
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• pp.714-719
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• 2009

In this paper, a compact antenna with band-rejected characteristic for Ultra-Wideband(UWB) applications is proposed. The designed antenna not only shows sufficient impedance bandwidth but has band-rejected characteristic for the frequency band of 5.15~5.825GHz limited by IEEE 802.11a and HIPERLAN/2. To obtain both properties of wideband band rejection, the techniques of a partial ground plane and embedded thin U-slot into planar radiator are used respectively. A designed antenna satisfied a VSWR less than 2:1 for the frequency band of 3.1~10.3GHz with band rejection of 4.90~5.92GHz.

• ETRI Journal
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• 제40권5호
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• pp.561-569
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• 2018

Modern communication systems employ wideband antennas with circular polarization (CP) radiation. In this work, asymmetric modified bow-tie (ABT) and symmetric modified bow-tie (SBT) slotted circularly polarized single-point probe-fed circular patch antennas with dimensions of $40mm{\times}40mm$ for wideband applications are proposed. A 10 dB RL bandwidth of 350 MHz with CP, 3 dB axial ratio (AR) bandwidth of 100 MHz, peak gain of 4.9 dBic, and 10 dB RL bandwidth of 530 MHz with CP, 3 dB AR bandwidth of 140 MHz, peak gain of 5 dBic are obtained for ABT and SBT slotted circular patch antennas, respectively. The proposed SBT slotted patch is scaled up and down to $50mm{\times}50mm$ and $30mm{\times}30mm$, respectively. The proposed scaled-up version offers 10 dB RL and 3 dB AR bandwidths of 340 MHz and 80 MHz, with a peak gain of 5 dBic. The scaled-down version offers 10 dB RL and 3 dB AR bandwidths of 710 MHz and 180 MHz, with a peak gain of 5.25 dBic. These prototypes are suitable to work in IEEE 802.11a WLAN, ISM, and IEEE 802.11ac applications. The measured and simulated results are then discussed and compared.

• Journal of the Institute of Electronics Engineers of Korea TC
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• 제46권2호
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• pp.66-72
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• 2009

In this paper, an efficient frequency offset synchronization structure for OFDM(Orthogonal Frequency Division Multiplexing) is proposed. Conventional CORDIC(Coordinate Rotation Digital Computer) algorithm for frequency offset synchronization utilizes two CORDIC hardware i.e., one is vector mode for phase estimation, the other is rotation mode for compensation. But proposed structure utilizes one CORDIC hardware and divider. Through simulation, it is shown that hardware implementation complexity is reduced compared with conventional structures. The Verilog-HDL coding and front-end chip implementation results for the proposed structure show 22.1% gate count reduction comparison with those of the conventional structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제7권8호
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• pp.1644-1652
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• 2003

In this paper, we have analyzed that interference effect between wireless LAN(IEEE 802.11 a) and radar system in 5㎓ band. Recently, Korea frequency Authority is considering the frequency allocation of wireless LAN system about 5㎓ band that is previously used in radar system. The co­existence occurs interference problem between wireless LAN and radar system, so it is required to analyze the effect of co­channel interference. Accordingly, the frequency allocation could be predicted for wireless LAN system in 5㎓ band and the interference effect has been analyzed by simulation with the radar signal modeling. Simulation results which are presented by PER and EVM show that high SIR(20 ㏈) is required to achieve the target PER about 10­1.