• Communications of the Korean Mathematical Society
• /
• v.27 no.4
• /
• pp.665-668
• /
• 2012

For a given graph G we consider a set S(G) of all symmetric matrices A = [$a_{ij}$] whose nonzero entries are placed according to the location of the edges of the graph, i.e., for $i{\neq}j$, $a_{ij}{\neq}0$ if and only if vertex $i$ is adjacent to vertex $j$. The minimum rank mr(G) of the graph G is defined to be the smallest rank of a matrix in S(G). In general the computation of mr(G) is complicated, and so is that of the maximum multiplicity MaxMult(G) of an eigenvalue of a matrix in S(G) which is equal to $n$ - mr(G) where n is the number of vertices in G. However, for trees T, there is a recursive formula to compute MaxMult(T). In this note we show that this recursive formula for MaxMult(T) also computes the path cover number $p$(T) of the tree T. This gives an alternative proof of the interesting result, MaxMult(T) = $p$(T).

• Communications of the Korean Mathematical Society
• /
• v.35 no.1
• /
• pp.1-12
• /
• 2020

A pathos block line cut-vertex graph of a tree T, written P BL_c(T), is a graph whose vertices are the blocks, cut-vertices, and paths of a pathos of T, with two vertices of P BL_c(T) adjacent whenever the corresponding blocks of T have a vertex in common or the edge lies on the corresponding path of the pathos or one corresponds to a block B_i of T and the other corresponds to a cut-vertex c_j of T such that c_j is in B_i; two distinct pathos vertices P_m and P_n of P BL_c(T) are adjacent whenever the corresponding paths of the pathos P_m(v_i, v_j) and P_n(v_k, v_l) have a common vertex. We study the properties of P BL_c(T) and present the characterization of graphs whose P BL_c(T) are planar; outerplanar; maximal outerplanar; minimally nonouterplanar; eulerian; and hamiltonian. We further show that for any tree T, the crossing number of P BL_c(T) can never be one.

• Journal of Korea Multimedia Society
• /
• v.25 no.11
• /
• pp.1643-1652
• /
• 2022

Most of the existing machine reading research has used Recurrent Neural Network (RNN) and Convolutional Neural Network (CNN) algorithms as networks. Among them, RNN was slow in training, and Question Answering Network (QANet) was announced to improve training speed. QANet is a model composed of CNN and self-attention. CNN extracts semantic and syntactic information well from the local corpus, but there is a limit to extracting the corresponding information from the global corpus. Graph Convolutional Networks (GCN) extracts semantic and syntactic information relatively well from the global corpus. In this paper, to take advantage of this strength of GCN, we propose I-QANet, which changed the CNN of QANet to GCN. The proposed model performed 1.2 times faster than the baseline in the Stanford Question Answering Dataset (SQuAD) dataset and showed 0.2% higher performance in Exact Match (EM) and 0.7% higher in F1. Furthermore, in the Korean Question Answering Dataset (KorQuAD) dataset consisting only of Korean, the learning time was 1.1 times faster than the baseline, and the EM and F1 performance were also 0.9% and 0.7% higher, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.149-150
• /
• 2007

ONO(Oxide-Nitride-Oxide)구조는 기억소자의 전하보유 능력을 향상시키기 위해 도입된 게이트 절연막이다. 본 연구에서는 ELA(Excimer Laser Annealing)방법으로 비정질 실리콘을 결정화 시켜서 그 위에 NVM(Nonvolatile Memory)소자를 만들어 전기적 특성을 측정하여 결과를 나타내었다. 실험 결과 같은 크기의 $V_D$에서 $V_G$를 조절함으로써 $I_D$의 크기를 조절할 수 있었다. $V_G-I_D$ Graph에서는 $I_{on}$과 $I_{off}$, 그리고 Threshold Voltage를 알 수 있었다. $I_{on}/I_{off}$ Ratio는 $10^3-10^4$이다. $V_G-I_D$ Graph에서는 게이트에 인가하는 Bias의 양을 통해서 Threshold Voltage의 크기를 조절할 수 있었다. 이는 Trap되는 Charge의 양을 임의로 조절할 수 있다는 것을 의미하며, 이러한 Programming과 Erasing의 특성을 이용하여 기억소자로서의 역할을 수행하게 된다.

• Journal of applied mathematics & informatics
• /
• v.22 no.1_2
• /
• pp.21-38
• /
• 2006

Programmed grammars, one of the most important and well investigated classes of grammars with context-free rules and a mechanism controlling the application of the rules, can be described by graphs. We investigate whether or not the restriction to special classes of graphs restricts the generative power of programmed grammars with erasing rules and without appearance checking, too. We obtain that Eulerian, Hamiltonian, planar and bipartite graphs and regular graphs of degree at least three are pr-universal in that sense that any language which can be generated by programmed grammars (with erasing rules and without appearance checking) can be obtained by programmed grammars where the underlying graph belongs to the given special class of graphs, whereas complete graphs, regular graphs of degree 2 and backbone graphs lead to proper subfamilies of the family of programmed languages.

• Bulletin of the Korean Mathematical Society
• /
• v.37 no.4
• /
• pp.649-657
• /
• 2000

The 2-step competition graph of D has the same vertex set as D and an edge between vertices x and y if and only if there exist (x, z)-walk of length 2 and (y, z)-walk of length 2 for some vertex z in D. The 2-step competition number of a graph G is the smallest number k such that G together with k isolated vertices is the 2-step competition graph of an acyclic digraph. Cho, et al. showed that the 2-step competition number of a path of length at least two is two. In this paper, we characterize all the minimal acyclic digraphs whose 2-step competition graphs are paths of length n with two isolated vertices and construct all such digraphs.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1463-1466
• /
• 1987

The problem of generating minimal area CMOS functional cell layout can be converted to that of decomposing the transistor connection graph into a minimum number of subgraphs, each having a pair of Euler paths with the same sequence of input labels on the N-graph and P-graph, which are portions of the graph corresponding to NMOS and PMOS parts respectively. This paper proposes a heuristic algorithm which yields a nearly minimal number of Euler paths from the path representation formula which represents the give a logic function. Subpath merging is done through a list processing scheme where the pair of paths which results in the lowest cost is successively merged from all candidate merge pairs until no further path merging and further reduction of number of subgraphs are possible. Two examples were shown where we were able to further reduce the number of interlaces, i.e., the number of non-butting diffusion islands, from 3 to 2, and from 2 to 1, compared to the earlier work [1].

• Journal of Communications and Networks
• /
• v.15 no.4
• /
• pp.407-410
• /
• 2013

Secret sharing is that a dealer distributes a piece of information (called a share) about a secret to each participant such that authorized subsets of participants can reconstruct the secret but unauthorized subsets of participants cannot determine the secret. In this paper, an access structure can be represented by a label graph G, where a vertex denotes a participant and a complete subgraph of G corresponds to a minimal authorized subset. The vertices of G are labeled into distinct vectors uniquely determined by the maximum prohibited structure. Based on such a label graph, a verifiable secret sharing scheme realizing general access structures is proposed. A major advantage of this scheme is that it applies to any access structure, rather than only structures representable as previous graphs, i.e., the access structures of rank two. Furthermore, verifiability of the proposed scheme can resist possible internal attack performed by malicious participants, who want to obtain additional shares or provide a fake share to other participants.

• Journal of the Korea Society of Computer and Information
• /
• v.3 no.4
• /
• pp.44-48
• /
• 1998

In this paper proposed Component Synthesis Algorithm(CSA) for mapping described HDL to RT component of given library. CSA transform I/O variables of HDL and relation of operators to control/data flow graph(CDFG) that consists of graph, reduce the size of graph, compute the cost, the bound, and the method that use compatibility graph(CG), and then mapping to component. Component synthesis used branch-and-bound algorithm. The result that synthesis using CSA algorithm was proved that this result and the cost of the manual were indentified.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3B
• /
• pp.183-198
• /
• 2006

We define the incomplete medium sharing system as a multi-channel shared medium communication system where constraints are imposed to the set of channels that may be allocated to some transmitter-receiver node pairs. To derive a centralized MAC scheme of a incomplete medium sharing system, we address the problem of optimal channel allocation The optimal channel allocation problem is then translated into a max-flow problem in a multi-commodity flow graph, and it is shown that the optimal solution can then be obtained by solving a linear programming problem. In addition, two suboptimal channel allocation schemes are proposed to bring down the computational complexity to a practical/feasible level; (1) one is a modified iSLIP channel allocation scheme, (2) the other is sequential channel allocation scheme. From the results of a extensive set of numerical experiments, it is found that the suboptimal schemes evaluate channel utilization close to that of the optimal schemes while requiring much less amount of computation than the optimal scheme. In particular, the sequential channel allocation scheme is shown to achieve higher channel utilization with less computational complexity than . the modified iSLIP channel allocation scheme.