• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1029-1034
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• 2010

For All Digital QPSK receivers, a phase recovery scheme is required to fix the arbitrarily rotated I/Q quadrature signals due to the transmission path and clock mismatch between the transmitter and the receiver. The conventional Costas phase recovery loop scheme requires a separate AGC(Automatic Gain Control) to obtain the performance independent of input signal power. This paper proposes a simple scheme which separates the phase and amplitude of the input signal via CORDIC algorithm and performs the phase recovery and amplitude compensation simultaneously. The proposed scheme can considerably reduce the logic resources in hardware implementation, has been verified by C++ and Model Sim simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.7-15
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• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.35-40
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• 2013

In this paper, we propose a new image rejection receiver architecture using simultaneously the high-side and low-side injected LO signals. The proposed architecture has a lower noise figure (NF) performance and a higher linearity characteristic than the previous receiver architecture using a single LO signal. Also, the proposed receiver shows a higher IRR performance about 6dB than that of the previous Weaver image rejection architecture even though the same gain and phase errors between I-path and Q-path exist. To verify these characteristics, we derive an IRR formular of the proposed architecture as a function of mismatch parameters. And we demonstrate its formular's usefulness through the system simulation. Therefore, the proposed architecture will be widely used to implement the image rejection receiver due to its higher IRR performance.