• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1241-1246
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• 2004

The verification confirms a correspondence between requirements and a specification before implementing. The problem in the formal method verifying a protocol specification using model checking is that the protocol behaviors must be always specified in L TS(Label Transition System). But if Region Automata is applied to the model checking, it is enable to verify whether properties are true on specification specified in I/O FSM(Input/Output Finite State Machine) as well as LTS. In this paper, we verify the correctness of rail signal control protocol type 1 specified in I/O FSM by using model checking method and region automata. This removes many errors and ambiguities of an informal method used in the past and saves down expenditures and times required in the protocol development. Therefore it is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling system by using the proposed verification methods.

• Journal of Korea Multimedia Society
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• v.1 no.1
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• pp.109-119
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• 1998

This paper describes a research result on automatic generation of Abstract Test Suite from INAP protocol in formal specifications by applying many existing related algorithms such as Rural Chinese Postman Tour and UIO sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence concepts. We use the I/O FSM generated from SDL specifications and a characterizing sequence, called UIO sequence, is defined for the I/O FSM. The UIO sequence is combined with the concept of Rural Chinese Postman tour to obtain an optimal test sequence. It also proposes an estimation methodology of the fault courage for the Test Suite obtained by our method and their translation into the standardized test notation TTCN.

• Electronics and Telecommunications Trends
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• v.13 no.6 s.54
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• pp.94-107
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• 1998

연구 개발의 주된 내용은 SDL(Specification Description Language)을 위한 정형기법 지원도구 중 명세상에서 행위 부분에 대한 동적 특성을 검정하는 검정기 개발이다. 모델 검정기는 해당 프로토콜에 대해 생성된 중간 모델 I/O FSM(Input/Output Finite State Machine)에 Modal-calculus에 의해 검정대상인 deadlock, livelock, reachability 및 liveness에 대한 표현과 I/O FSM에 대해 해당 알고리즘 적용 및 분석 기능을 C++언어로 구현하였다. 또한 SDL Editer 기능과 관련된 도구들과 통합하여 사용자들이 쉽고 편하게 쓸 수 있도록 환경 및 통합 모듈을 구현한다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.552-562
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• 1997

This paper proposes a formal method on confromance testing for INAP(AIN) test sequence generation by optimization technique.In order to implement and prove the dffectiveness of the proposed method,we specify the SRSM of INAP protocol SRF in SDL and generate I/O FSM by using our S/W tool. We generate an opti-mal test sequence by applying our method our method to this reference I/O FSM. We prove experimentally that the length of the generated test sequence by our method is more effective and shorter(i.e 32% improved)than the one geverated by UIO method,and estimate that The test coverage space of our test sequence is larger that of UIO method.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.358-362
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• 2004

Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for a formal railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for a railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment).

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.21-30
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• 2016

Recently manufacturing companies have used PLC control programs popularly for their automated production systems. Since the life cycle of production process is not so long, the change of the production lines occur frequently. Most of changes happen with modification of the position information and control process of the equipment. PLC control program is also modified based on the fundamental process. Therefore, to verify new PLC program by configuring virtual space according to real environment is needed. In this paper we show a logical modeling method, based on Timed-FSA useful for sequence control and dead-lock prevention. There is a problem wasting user's labor and time when defining a variety of states in a device. To overcome this problem, we propose an extended I-O model based on existing methods by adding a token concept of Petri Nets. Also we will show the usability of the extended I-O modeling through user study.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1485-1492
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• 1999

대규모 시스템 명세의 올바름을 검증하기 위한 유한 상태 LTS에 기반을 둔 CTL논리 적용에 있어 가장 큰 문제점은, 시스템 내부의 병렬 프로세스간의 상호작용으로 인한 상태폭발이다. 그러나 Modal mu-calculus 논리를 시스템 안전성 및 필연성 특성 명세에 사용하면, 행위에 의한 순환적 정의가 가능하므로 상태폭발 문제가 해결 가능하다. 본 논문에서는 LTS로 명세화된 통신 프로토콜 시스템 모델의 안전성 및 필연성 특성을 모형 검사 기법에 의해 검증함에 있어, 시제 논리로 사용된 Modal mu-calculus 안전성 및 필연성 논리식과 CTL 의 안전성 및 필연성 논리식의 극한값이 동일함을 두 논리식을 만족하는 상태 집합이 같다는 것을 보임으로써 증명한다. 증명된 결과는 I/O FSM 모델로 표현된 통신 프로토콜의 안전성 및 필연성 검사를 위해 이론적인 기반으로서, 컴퓨터를 이용한 모형검사 기법에 효과적인 방법으로 응용이 가능하다.Abstract In applying CTL-based model checking approach to correctness verification of large state transition system specifications, the major obstacle is the combinational explosion of the state space arising due to interaction of many loosely coupled parallel processes. If, however, the modal mu-calculus viewed as a CTL-based logic with recursion, is used to specify the safety and liveness property of a given system, it is possible to resolve this problem. In this paper, we discuss the problem of verifying communication protocol system specified in LTS, and prove that a logic expression specifying safety and liveness in modal mu-calculus is semantically identical to the maximum value of the expression in CTL. This relation is verified by the proof that the sets of states satisfying the two logic expressions are equivalent. The proof can be used as a theoretical basis for verifying safety and liveness of communication protocols represented as I/O FSM model.

• The Transactions of the Korea Information Processing Society
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• v.4 no.5
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• pp.1327-1336
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• 1997

Test generation from the communication protocol specified in I/OFSM protocol is based on the asumption that the specification S and implemenataiton I are storngly, connected,minmal and deterministic.In this paper,we identify why these asumptions are necessary for minimal test cases genration from I/OFSM protocol speci-fication,and we propose a graph Rewriting System and its application to the specification I/OFSM for verifying its storng cinnectivity.We prove that the suggested algorithm is more dffcient thah the traditional strongly connected compoment find algorithm.

• Electronics and Telecommunications Trends
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• v.14 no.2 s.56
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• pp.26-37
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• 1999

ATM 프로토콜 적합성 시험 생성 도구 개발을 프로토콜 개발 통합환경과 연계하여 개발한다. 즉 생성된 I/O FSM 중간모델을 대상으로 연구된 가장 짧은 길이의 시험 스위트(test suite)를 생성하는 알고리즘을 편리하고 용이하게 적용하기 위해 데이터 구조화 및 컴퓨터 내에서의 표현 등을 위한 초기화 작업기능을 SDL Editor & Simulator를 활용하여 확인한다. 그리고 ATS(Abstract Test Suite) 생성은 UIO 시퀀스를 결정하고, TUT와 도착상태의 UIO 시퀀스를 결합한 시험 subsequence 생성과 symmetric argumentation 과정을 거처 RCP(Rural Chinese Postman) Tour 생성 알고리즘 구현을 통해 완전 시험 스위트 생성도구를 개발하고, 프로토콜 검정기와 연계하여 통합된 환경에서 사용할 수 있도록 개발한다.