• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.7-12
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• 2005

A compact microstrip band-selective filter for ultra-wideband (UWB) radio system is proposed. The filter combines the traditional short-circuited stub highpass filter and coupled resonator bandstop filter on both sides of the mitered 50-ohm microstrip line. To realize the pseudo-highpass filtering characteristic over UWB frequency band (3.1 GHz to 10.6 GHz), a distributed highpass filter scheme is adopted. Three coupled resonators are utilized to obtain the band stop function at the desired frequency band. By meandering the coupled resonators, there is 29% reduction in footprint compared to the traditional bandstop filter using L-shaped resonators. The measured results show that the filter has a wide passband of 146.7 % (2.1 GHz to 10.15 GHz) with low insertion loss and the stop band of 7.42 % (5.32 GHz to 5.73 GHz) for 3-dB bandwidth. The measured group delay is less than 0.7 ns within the passband except the rejection band.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2458-2467
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• 1994

This paper proposes a new design method for obtaining the impulse responses which satisfy the prescribed conditions designing for maximally flat FIR lowpass filters and highpass filters. The bandpass filters and band-reject filters have been directly derived from the addition and subtraction of impulse responses of a lowpass filter and a highpass filter. The two-dimensional maximally flat FIR lowpass filter, highpass filters, bandpass filters and band-reject filters with zero-phase have been designed by transforming the impulses of the one-dimensional filters designed in this research, which do not destroy lines and edges at the image signal processing.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.353-356
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• 2002

In this paper, we design an efficient, scalable one-dimensional discrete wavelet transform (1DDWT) filter using data reorder unit (DRU). At each level, the required hardware is optimized by sharing multipliers and adders because the input rate is reduced by a factor of two at each level due to decimation. The proposed architecture shows 100% hardware utilization by balancing hardware with input rate. Furthermore, sharing the coefficients of the highpass and the lowpass filters using the mirror filter property reduces the number of multipliers and adders by half. We designed a scalable DRU that efficiently reorders and feeds inputs to highpass and lowpass filters. The proposed DRU-based architecture is so regular and scalable that it can be easily extended to an arbitrary 1D DWT structure with M taps and J levels. Compared to other architectures, the proposed DWT filter shows efficiency in performance with relatively less hardware.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.89-94
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• 2006

A compact microstrip band-selective filter for ultra-wideband(UWB) radio system is proposed. The filter combines the traditional short-circuited stub highpass filter and coupled resonator band-stop filter on both sides of the mitered 50-ohm microstrip line. To realize the pseudo-highpass filtering characteristic over UWB frequency band(3.1 GHz to 10.6 GHz), a distributed highpass filter scheme is adopted. Three coupled resonators are utilized to obtain the band stop function at the desired frequency band. By meandering the coupled resonators, there is $29\;\%$ size reduction in footprint compared to the traditional band-stop filter using L-shaped resonators. The measured results show that the filter has a wide passband of $146.7\;\%$(2.1 GHz to 10.15 GHz) with low insertion loss and the stop band of $10.04\;\%$(5.2 GHz to 5.75 GHz) for 3-dB bandwidth. The measured group delay is less than 0.7 ns within the passband except the rejection band.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.6
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• pp.96-103
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• 1999

This paper proposes efficient VLSI architecture for computation of the 1-D discrete wavelet transform (DWT). The proposed VLSI architecture computes the wavelet lowpass and highpass output sequences using the product term anhm, $n,m{\ge}0$, where an and hm denote the imput sequence and the wavelet lowpass filter coefficient, respectively. Whereas the conventional architectures compute the lowpass and highpass output sequences using the product terms anhm and angm, respectively, where gm denotes the wavelet highpass filter coefficient. The proposed architecture is applied to computation of the Daubechies 4-tap wavelet transform using the relationships between the Daubechies wavelet filter coefficients. Performance comparison of various architectures for computation of the 1-D DWT are presented. Note that the proposed architecture does not require extra processing units whereas the conventional architectures need them. Also it is modeled in very high speed integrated circuit hardware description language (VHDL) and simulated to show its functional validity.

• ETRI Journal
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• v.26 no.4
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• pp.292-296
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• 2004

In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions - all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters $\omega_0$ and $\omega_0/Q$. No element matching conditions are imposed. Both its active and passive sensitivities are low.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.99.2-99
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• 2001

An electronically tunable current-mode second-order multifunctional filter is described in this paper. The proposed filter consists of two four-terminal floating nullors (FTFNs), two dual-output OTAs and two grounded capacitors. The circuit can simultaneously realize the lowpass, bandpass and highpass current transfer functions from the same configuration without changing the circuit configuration and elements. The natural angular frequency we and the parameter wo/Q can be orthogonally controlled through adjusting the transconductance gain of OTA. PSPICE simulation results are employed to confirm the circuit performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1685-1688
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• 2003

The modem multimedia applications which are video Processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the proposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process image data on tile high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33㎒.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.223-227
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• 1996

In this paper we propose an adaptive fast image restoration filter, which is suitable for reducing the blocking artifacts in the compressed image in real-time. The proposed restoration filter is based on the observation that quantization operation in a series of coding process is a nonlinear and many-to-one mapping operator. And then we propose an approximated version of constrained optimization technique as a restoration process for removing the nonlinear and space varying degradation operator. We also propose a novel block classification method for adaptively choosing the direction of a highpass filter, which serves as a constraint in the optimization process. The proposed classification method adopts the bias-corrected maximized likelihood, which is used to determine the number of regions in the image for the unsupervised segmentation. The proposed restoration filter can be realized either in the discrete Fourier transform domain or in the spatial domain in the form of a truncated finite impulse response (FIR) filter structure for real-time processing. In order to demonstrate the validity of the proposed restoration filter experimental results will be shown.