• Title/Summary/Keyword: High-speed Operation

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Height perception of large airplane pilots during landing flare (대형 비행기 조종사의 착륙 조작 시의 높이지각)

  • Kim, Yong-Seok;Sohn, Young-Woo;Park, Soo-Ae;Kim, Chil-Young
    • Science of Emotion and Sensibility
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    • v.10 no.4
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    • pp.539-554
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    • 2007
  • Pilots of large airplanes have to land their airplanes with insufficient visual information because of high approach speed, high vertical velocity and high location or altitude of the cockpits from the runway intending to touch down. This study verifies that, due to the insufficient information, large airplane pilots can't exactly perceive height of their airplanes during the flare. Study 1 explored whether it's possible for the pilots to accurately perceive height with the static visual cues only. We showed them pictures of the runway taken from the pilot's pionts of view and asked them to assess the height of the airplanes. They determined exact height of the airplanes at the height of 85 feet, but they could not, at lower than 55 feet which is the flare preparation altitude. Study 2 explored whether it's possible for the pilots to accurately perceive height when dynamic cues were added to the static visual cues. We showed them videos of the runway taken from the pilot's pionts of view. With more cues they determined exact height of the airplanes at the height of 50 feet, but they could not, at the altitude of lower than 30 feet which is the flare altitude. As experience is believed to be a major factor which affects interpretation of the visual cues, we compared the accuracy of the assessment of the experienced captions and that of the in-experienced first officers. We found there was no significant difference between them.

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Improvement of KOMPSAT-5 Sea Surface Wind with Correction Equation Retrieval and Application of Backscattering Coefficient (KOMPSAT-5 후방산란계수의 보정식 산출 및 적용을 통한 해상풍 산출 결과 개선)

  • Jang, Jae-Cheol;Park, Kyung-Ae;Yang, Dochul;Lee, Sun-Gu
    • Korean Journal of Remote Sensing
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    • v.35 no.6_4
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    • pp.1373-1389
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    • 2019
  • KOMPSAT-5 is the first satellite in Korea equipped with X-band Synthetic Aperture Radar (SAR) instrument and has been operated since August 2013. KOMPSAT-5 is used to monitor the global environment according to its observation purpose and the availability of KOMPSAT-5 is also highlighted as the need of high resolution wind data for investigating the coastal region. However, the previous study for the validation of wind derived from KOMPSAT-5 showed that the accuracy is lower than that of other SAR satellites. Therefore, in this study, we developed the correction equation of normalized radar cross section (NRCS or backscattering coefficient) for improvement of wind from the KOMPSAT-5 and validated the effect of the equation using the in-situ measurement of ocean buoys. Theoretical estimated NRCS and observed NRCS from KOMPSAT-5 showed linear relationship with incidence angle. Before applying the correction equation, the accuracy of the estimated wind speed showed the relatively high root-mean-square errors (RMSE) of 2.89 m s-1 and bias of -0.55 m s-1. Such high errors were significantly reduced to the RMSE of 1.60 m s-1 and bias of -0.38 m s-1 after applying the correction equation. The improvement effect of the correction equation showed dependency relying on the range of incidence angle.

Effectiveness Analysis of HOT Lane and Application Scheme for Korean Environment (HOT차로 운영에 대한 효과분석 및 국내활용방안)

  • Choi, Kee Choo;Kim, Jin Howan;Oh, Seung Hwoon
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.29 no.1D
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    • pp.25-32
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    • 2009
  • Currently, various types of TDM (Transportation Demand Management) policies are being studied and implemented in an attempt to overcome the limitations of supply oriented policies. In this context, this paper addressed issues of effectiveness and possible domestic implementation of the HOT lane. The possible site of implementation selected for this simulation study is part of the Kyung-bu freeway, where a dedicated bus lane is currently being operated. Minimum length of distance required in between interchanges and access points of the HOT lane for vehicles to safely enter and exit the lane, and traffic management policies for effectively managing the weaving traffic trying to enter and exit the HOT lane were presented. A 5.2km section of freeway from Ki-heuing IC to Suwon IC and a 8.3km section from Hak-uei JC to Pan-gyo JC have been selected as possible sites of implementation for the HOT lane, in which congestion occurs regularly due to the high level of travel demand. VISSIM simulation program has been used to analyze the effects of the HOT lane under the assumption that one-lane HOT lane has been put into operation in these sections and that the lane change rate were in between 5% to 30%. The results of each possible scenario have proven that overall travel speed on the general lanes have increased as well by 1.57~2.62km/h after the implementation of the HOT lane. It is meaningful that this study could serve as a basic reference data for possible follow-up studies on the HOT lane as one effective method of TDM policies. Considering that the bus travel rate would continue increase and assuming the improvement in travel speed on general lanes, similar case study can be implemented where gaps between buses on bus lane are available, as a possible alternative of efficient bus lane management policies.

A 1280-RGB $\times$ 800-Dot Driver based on 1:12 MUX for 16M-Color LTPS TFT-LCD Displays (16M-Color LTPS TFT-LCD 디스플레이 응용을 위한 1:12 MUX 기반의 1280-RGB $\times$ 800-Dot 드라이버)

  • Kim, Cha-Dong;Han, Jae-Yeol;Kim, Yong-Woo;Song, Nam-Jin;Ha, Min-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.98-106
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    • 2009
  • This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.

The Study for an Improved Methodology of Rail Investment Rating System (철도투자평가체계 개선방안의 고찰)

  • Roh, Byoung-Kuk;Kim, Young-Bea;Jin, Hak-Ki
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.2192-2204
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    • 2011
  • Recently, The government is actively transit road-oriented Traffic System to the eco-friendly and high-efficiency railroad-oriented transportation system for the sustainable green growth. The second plan of Nationwide Railway Network which has been officially announced rearrange to integration, multi-core, open architecture country by the railway network and integrate to the one mega city that rink an important city in one hour 30 minute. But the railroad industry is disadvantageous when it compares with the road industry on the ground that railroad industry peculiarities(a cost-benefit analysis, an environment value, etc) have not reflected in the (preliminary) feasibility study for SOC industry. The government establish Improved methodology of Rail Investment Rating System and improved preliminary feasibility study in railroad project by introduction many content(analysis periods, rate of discount, the benefits of shortening of transit hours, the estimation of traffic accident reduction benefits, investment cost of vehicle substitution and operation and maintenance cost of high speed rail) about the Improved methodology of Rail Investment Rating System. This study is intended to consideration the key content that was included in the Improved methodology of Rail Investment Rating System. In addition, the points to be considered for additional study have been reviewed in this study. We hope we will carry out make a reasonable and objective Rail Investment Rating System and to perform the railway industry of the virtuous cycle such improvement plans are reflected at a hereafter railroad section.

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Design and Implementation of Asynchronous Memory for Pipelined Bus (파이프라인 방식의 버스를 위한 비 동기식 주 기억장치의 설계 및 구현)

  • Hahn, Woo-Jong;Kim, Soo-Won
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.11
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    • pp.45-52
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    • 1994
  • In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

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Study for Fracture in the Last Stage Blade of a Low Pressure Turbine (화력발전용 저압터빈 최종 단 블레이드에 대한 파손 연구)

  • Lee, Gil Jae;Kim, Jae Hoon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.40 no.4
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    • pp.423-428
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    • 2016
  • The last stage blades of a low pressure (LP) turbine get frequently fractured because of stress corrosion cracking. This is because they operate in a severe corrosive environment that is caused by the impurities dissolved in condensed steam and high stress due to high speed rotation. To improve the reliability of the blades under severe conditions, 12% Cr martensitic stainless steel, having excellent corrosion resistance and higher strength, is widely used as the blade material. This paper shows the result of root cause analysis on a blade which got fractured suddenly during normal operation. Testing of mechanical properties and microstructure examination were performed on the fractured blade and on a blade in sound condition. The results of testing of mechanical properties of the fractured blade showed that the hardness were higher but impact energy were lower, and were not meeting the criteria as per the material certificate specification. This result showed that the fractured blade became embrittled. The branch-type crack was found to have propagated through the grain boundary and components of chloride and sulfur were detected on the fractured surface. Based on these results, the root cause of fracture was confirmed to be stress corrosion cracking.

Simulator for 3 Phase Induction Motor with LCL Filter and PWM Rectifier (LCL 필터와 PWM 정류기를 이용한 3상 유도전동기의 시뮬레이터)

  • Cho, Kwan Yuhl;Kim, Hag Wone
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.11
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    • pp.861-869
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    • 2020
  • A dynamo set for a high-power induction motor drive is expensive and needs a long time to manufacture. Therefore, the development of a simulator that functions as the induction motor and load equipment is required. A load simulator of an inverter for a high-power three-phase induction motor consists of a reactor and three-phase PWM inverter. Therefore, it cannot simulate the dynamic characteristics of an induction motor and functions only as a load. In this paper, a real-time simulator is proposed to simulate a model of an induction motor and the load characteristics based on an LCL filter and three-phase PWM rectifier for a three-phase induction motor. The currents of a PWM inverter that simulate the stator currents of the motor are controlled by the inductor currents and capacitor voltages of the LCL filter. The capacitor voltages of the LCL filter simulate the induced voltages in the stator windings by the rotating rotor fluxes of the motor, and the capacitor voltages are controlled by the inductor currents and a PWM rectifier. The rotor currents, the stator and rotor flux linkages, the electromagnetic torque, the slip frequency, and the rotor speed are derived from the inverter currents and the motor parameters. The electrical and mechanical model characteristics and the operation of vector control were verified by MATLAB/Simulink simulation.

FAST : A Log Buffer Scheme with Fully Associative Sector Translation for Efficient FTL in Flash Memory (FAST :플래시 메모리 FTL을 위한 완전연관섹터변환에 기반한 로그 버퍼 기법)

  • Park Dong-Joo;Choi Won-Kyung;Lee Sang-Won
    • The KIPS Transactions:PartA
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    • v.12A no.3 s.93
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    • pp.205-214
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    • 2005
  • Flash memory is at high speed used as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because flash memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of flash memory is impossible to be done. In order to make an overwrite possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of flash memory highly. In order to solve this problem the flash memory controller maintains a system software module called the flash translation layer(FTL). Of many proposed FTL schemes, the log block buffer scheme is best known so far. This scheme uses a small number of log blocks of flash memory as a write buffer, which reduces the number of erase operations by overwrites, leading to good performance. However, this scheme shows a weakness of low page usability of log blocks. In this paper, we propose an enhanced log block buffer scheme, FAST(Full Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the log block buffer scheme.

Japan's Missile Detection Capability using Electromagnetic Wave in free space (일본의 자유공간에서 전자파를 이용한 미사일 탐지능력)

  • Lee, Yongsik
    • Journal of Satellite, Information and Communications
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    • v.12 no.4
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    • pp.78-86
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    • 2017
  • Japan has a lot of interest about weapons systems development of surrounding national and has invested heavily in securing intelligence assets to get information about them, because of conflict issues between Japan and Russia with four northern islands, China with Senkaku Islands and entry policy into the Pacific. Japan has used a large budget to detect and intercept ballistic missile for reasons of the launch of the Taepodong missile in 1998. After took over SIGINT equipments which U.S. force had operated in 1950s~1960s, Japan made a technological analysis and advanced IT technology to produce superior equipments. Japan's SDF has installed them in 19 locations across Japan. In addition, Japan's JASDF has installed advanced early warning RADAR to detect aircraft and high speed ballistic missile entering JADIZ with S-band in 28 locations across Japan. It is possible to detect missile launch preparations, engine tests, and launch moments at any time for operation of 6 satellites high resolution reconnaissance system and 6 aegis ships. In close cooperation with the US, Japan is accessible to the SBIRS networks which detects the launch of a ballistic missile in neighboring countries. In the future, Because the United States wants Japan to act as part of the United States in East, south Asia, it is believed that the exchange of intelligence on the surrounding countries between two countries will be enhanced.