• International Journal of Korean Welding Society
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• v.2 no.2
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• pp.57-60
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• 2002

Generally, the laser vision sensor makes it possible design a highly reliable and precise range sensor at a low cost. When the laser vision sensor is applied to lap joint welding, however. there are many limitations. Therefore, a specially-designed hardware system has to be used. However, if the multi-lines are used instead of a single line, multi-range data .:an be generated from one image. Even under a set condition of 30fps, the generated 2D range data increases depending on the number of lines used. In this study, a laser vision sensor with a multi-line pattern is developed with conventional CCD camera to carry out high speed seam tracking in lap joint welding.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.3
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• pp.185-190
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• 2022

We propose a high speed data communication method for motor drive systems with fast control cycle in order to collect state variables of motor control without degrading control performance. Ethernet is chosen for communication device, and multi-core DSP architecture is exploited for communication processing load distribution. The communication program including network protocol stack and motor control program are assigned to two separate cores, and data between two cores are exchanged using interrupt-based inter-process communication mechanism, which enables to achieve a high-speed communication performance without degrading the motor control performance. The performance of developed communication method is demonstrated by real experiments using TCP, UDP and Raw Socket protocols in an experimental setup consisting of TI's TMS320F28388D motor control card and MS Windows PC.

• Journal of Information Processing Systems
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• v.16 no.4
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• pp.832-844
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• 2020

The degree of dispersion of a random variable can be described by the variance, which reflects the distance of the random variable from its mean. However, the time complexity of the traditional variance calculation algorithm is O(n), which results from full calculation of all samples. When the number of samples increases or on the occasion of high speed signal processing, algorithms with O(n) time complexity will cost huge amount of time and that may results in performance degradation of the whole system. A novel multi-step recursive algorithm for variance calculation of the time-varying data series with O(1) time complexity (constant time) is proposed in this paper. Numerical simulation and experiments of the algorithm is presented and the results demonstrate that the proposed multi-step recursive algorithm can effectively decrease computing time and hence significantly improve the variance calculation efficiency for time-varying data, which demonstrates the potential value for time-consumption data analysis or high speed signal processing.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.87-90
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• 2006

Nowadays, we can enjoy access to high speed network and advanced services of convergence between broadcasting and communication anywhere and anytime through a ubiquitous computing. So, now digital convergence devices come out constantly. These devices are required faster network environment for high speed data processing than before. In this paper, we describe the design of InfiniBnad network adapter, which is included two FPGA chipsets. When this adapter is installed to Digital Convergence Platform (DCP) network performance will be improved. The adapter includes 12channel serial ports for external communication and internally, uses PCI-Express bus. We have finished the test of high speed serial based network adapter through composing complete InfiniBand network and applied fabric management software. So, we have verified that it can be applied on DCP environment.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.12-15
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• 2020

Data access characteristics can directly affect the efficiency of the system execution. This research is to design an accurate predictor by using historical memory access information, where highly accessible data can be migrated from low-speed storage (SSD/HHD) to high-speed memory (Memory/CPU Cache) in advance, thereby reducing data access latency and further improving overall performance. For this goal, we design a locally weighted linear regression prefetch scheme to cope with irregular access patterns in large graph processing applications for a DARM-PCM hybrid memory structure. By analyzing the testing result, the appropriate structural parameters can be selected, which greatly improves the cache prefetching performance, resulting in overall performance improvement.

• Journal of IKEEE
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• v.19 no.3
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• pp.288-294
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• 2015

CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

• Journal of Information Processing Systems
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• v.13 no.4
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• pp.668-676
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• 2017

Recently, the importance of big data has been emphasized with the development of smartphone, web/SNS. As a result, MapReduce, which can efficiently process big data, is receiving worldwide attention because of its excellent scalability and stability. Since big data has a large amount, fast creation speed, and various properties, it is more efficient to process big data summary information than big data itself. Wavelet histogram, which is a typical data summary information generation technique, can generate optimal data summary information that does not cause loss of information of original data. Therefore, a system applying a wavelet histogram generation technique based on MapReduce has been actively studied. However, existing research has a disadvantage in that the generation speed is slow because the wavelet histogram is generated through one or more MapReduce Jobs. And there is a high possibility that the error of the data restored by the wavelet histogram becomes large. However, since the wavelet histogram generation system based on the MapReduce developed in this paper generates the wavelet histogram through one MapReduce Job, the generation speed can be greatly increased. In addition, since the wavelet histogram is generated by adjusting the error boundary specified by the user, the error of the restored data can be adjusted from the wavelet histogram. Finally, we verified the efficiency of the wavelet histogram generation system developed in this paper through performance evaluation.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.9-15
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• 2022

NAND flash memory is used as a medium for various storage devices due to its high data processing speed with low power consumption. However, since the read processing speed of data is about 10 times faster than the write processing speed, various studies are being conducted to improve the speed difference. In particular, flash dedicated buffer management policies have been studied to improve write speed. However, SSD(solid state disks), which has recently been used for various purposes, is more vulnerable to read performance than write performance. In this paper, we find out why read performance is slower than write performance in SSD composed of NAND flash memory and study buffer management policies to improve it. The buffer management policy proposed in this paper proposes a method of improving the speed of a flash-based storage device by analyzing the pattern of read data and applying a policy of pre-reading data to be requested in the future from NAND flash memory. It also proves the effectiveness of the read-ahead policy through simulation.

• The KIPS Transactions:PartC
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• v.11C no.2
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• pp.157-162
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• 2004

Recently, the growth of information infrastructure is getting fatter and faster. At the same time, the security accidents are increasing together. We have problem that do not handle traffic because we have the Intrusion Detection Systems in low speed environment. In order to overcome this, we need effective security analysis techniques that ran Processed data of high-capacity because high speed network environment. In this paper we proposed the Gigabit Intrusion Detection System for coordinated security function such as intrusion detection, response on the high speed network. We suggested the detection mechanism in high speed network environment that have pattern matching function based packet header and based packet data that is proceeded in system kernel area, we are shown that this mechanism was excellent until maximum 20 times than existing system in traffic processing performance.

• International Journal of Railway
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• v.2 no.4
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• pp.180-186
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• 2009

High speed railway challenge the design, construction and maintaining of traditional railway, many traditional design concepts have been changed. Transition of railway and bridge has two main problems. one is that different lines have different ability of resisting distortion in area of trial load, which was known that problem of smooth transition of stiffness, the other is that differential settlement between artificial structure and earth structure cause bending of railway. The two problems have effect on train moving. The principle of processing transition of railway and bridge is same in world, but it is difficult to find relationship between design standard of transition, vehicle performance, line standard, design speed and so on form documentation and data reports. Based on mechanics, the paper analyzed dynamic performance of transition of high speed railway, studied various rough elements which is effective to train moving, built mathematical model of interaction of train and transition of high speed railway and developed numerical simulation software. In various different work conditions, we did great quantity of numerical simulation, comprehensive analysis and performance analysis.