• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.58-58
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• 1999

The diamond films which can be applied to SOD (silicon-on-diamond) structure were deposited on Si(100) substrate using CO/H2 CH4/H2 source gases by microwave plasma chemical vapor deposition(MPCVD), and SOD structure have been fabricated by poly-silicon film deposited on the diamond/Si(100) structure y low pressure chemical vapor deposition(LPCVD). The phase of the diamond film, surface morpholog, and diamond/Si(100) interface were confirmed by X-ray diffraction(XRD), scanning electron microscopy(SEM), atomic force microscopy(AFM), and Raman spectroscopy. The dielectric constant, leakage current and resistivity as a function of temperature in films are investigated by C-V and I-V characteristics and four-point probe method. The high quality diamond films without amorphous carbon and non-diamond elements were formed on a Si(100), which could be obtained by CO/H2 and CH4/H2 concentration ratio of 15.3% and 1.5%, respectively. The (111) plane of diamond films was preferentially grown on the Si(100) substrate. The grain size of the films deposited by CO/H2 are gradually increased from 26nm to 36 nm as deposition times increased. The well developed cubo-octahedron 100 structure nd triangle shape 111 are mixed together and make smooth and even film surface. The surface roughness of the diamond films deposited by under the condition of CO/H2 and CH4/H2 concentration ratio of 15.3% and 1.5% were 1.86nm and 3.7 nm, respectively, and the diamond/Si(100) interface was uniform resistivity of the films deposited by CO/H2 concentration ratio of 15.3% are obtained 5.3, 1$\times$10-9 A/cm, 1 MV/cm2, and 7.2$\times$106 $\Omega$cm, respectively. In the case of the films deposited by CH4/H2 resistivity are 5.8, 1$\times$10-9 A/cm, 1 MV/cm, and 8.5$\times$106 $\Omega$cm, respectively. In this study, it is known that the diamond films deposited by using CO/H2 gas mixture as a carbon source are better thane these of CH4/H2 one.

• Journal of the Korean Vacuum Society
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• v.17 no.1
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• pp.73-79
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• 2008

In order to apply for transparent conductive oxide(TCO), we deposited ZnO thin films on the glass at room temperature by RF magnetron sputtering method. Deposition conditions for high transmittance and low resistivity were optimized in our previous studies. Under the deposition condition with the RF power of 200 W, target to substrate distance of 30 mm and working pressure of 5 mTorr, highly conductive($7.4{\times}10^{-3}{\Omega}cm$) and transparent(over 85%) ZnO films were prepared. Highly oriented ZnO film in the [002] direction were obtained with specifically designed ZnO targets. Systematic study on dependence of deposition parameters on electrical and optical properties of the as-grown ZnO films were mainly investigated in this work. And for application tests using these films as transparent conductive oxide anodes, wet chemical etching behaviors of ZnO films were also investigated using various chemicals. Wet-chemical etching behavior of ZnO films were investigated using various acid solutions. The concentrations of these different acid solutions were controlled to study the etching shapes and etching rate. ZnO films were anisotropically etched at various concentrations and wet etching led to crater-like surface structure. Also we firstly found that the etching rate and etching shapes of ZnO films strongly depended on the etchant concentrations (i.e. pH) and the etching rate is exponentially decreased with increasing pH values regardless of the acid etchants.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Journal of the Korean Vacuum Society
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• v.19 no.5
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• pp.360-364
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• 2010

Most research groups used two analysis methods (spectroscopy and nanotribology) to measure the mechanical properties of nano-materials: NMR (Nuclear Magnetic Resonance), IR (Infrared Spectroscopy), Raman Spectroscopy as the spectroscopy method and AFM (Atomic Force MicroScope), EFM (Electrostatic Force Microscope), KFM (Kelvin Force Microscope), Nanoindenter as the nanotribological one. Among these, the nano-indentation technique particularly has been recognized as a powerful method to measure the elastic modulus and the hardness. However, this technique are prone to considerable measurement errors with pressure conditions during measurement. In this paper, we measured the change of elastic modulus and hardness of an Al single crystal with the change of load, hold, and unload time, respectively. We found that elastic modulus and hardness significantly depend on load, hold, and unload time, etc. As the indent time was shortened, the elastic modulus value decreased while the hardness value increased. In addition, we found that elastic modulus value was more sensitive to indent load, hold, and unload time than the hardness value. We speculate that measurement errors of the elastic modulus and the hardness originate from the residual stress during indenting test. From our results, the elastic modulus was more susceptible to the residual stress than the hardness. Thus, we find that the residual stress should be controlled for the minimum measurement errors during the indenting test.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.221-221
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• 2013

Vertical LED (VLED) has been recognized as a way to obtain the high-power LED due to their advantages [1]. However, approximately 4% of the light generated from the active region is extracted, if the light extraction from side walls and back side is neglected because of Fresnel reflection (FR) and total internal reflection (TIR) [2,3]. In this study, the optical simulation of the VLED with the various microstructures was performed. Among them, the microlens having the diameter of 3 ${\mu}m$ and the height of 1.5 ${\mu}m$ shown the best result was chosen, and then, optimized microlens was formed on a GaN template using conventional semiconductor process. Various microstructures were proposed to improve the light extraction efficiency (LEE) of the VLED for the simulation. The LEE was simulated using LightTools based on a Monte Carlo ray tracing. The microstructures with hemisphere, cone, truncated and cylinder pattern having diameter of 3 ${\mu}m$ were employed on the top layer of the VLED respectively. The improvement of the LEE by using the microstructure is 87% for the hemisphere, 77% for the cone, 53% for the truncated, 21% for the cylinder, compared with the LEE of the flat surface at the reflectance of 85%. The LEE was increased by 88% at the height of 1.5 ${\mu}m$, compared with the LEE of the flat surface. We found that the microlens on the top layer is the most suitable for increasing the LEE. In order to apply the proposed microlens on n-GaN surface, we fabricated microlens on a GaN template. A photoresist array having hexagonal-closed packed microlens was fabricated on the GaN template. Then, optimization of etching the GaN template was performed using a dry etching process with ICP-RIE. The dry etching carried out using a gas mixture of Cl2 and Ar, each having a flow rate of 16 sccm and 10 sccm, respectively with RF power of 50 W, ICP power of 900 W and chamber pressure of 2 mTorr was the optimum etching condition as shown in Fig. 2(a).

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.5
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• pp.939-951
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• 2002

We propose a new multiscale Galerkin method based on interpolation wavelets for two-dimensional Poisson's and plane elasticity problems. The major contributions of the present work are: 1) full multiresolution numerical analysis is carried out, 2) general boundaries are handled by a fictitious domain method without using a penalty term or the Lagrange multiplier, 3) no special integration rule is necessary unlike in the (bi-)orthogonal wavelet-based methods, and 4) an efficient adaptive scheme is easy to incorporate. Several benchmark-type problems are considered to show the effectiveness and the potentials of the present approach. is 1-2m/s and impact deformation of the electrode depends on the strain rate at that velocity, the dynamic behavior of the sinter-forged Cu-Cr is a key to investigate the impact characteristics of the electrodes. The dynamic response of the material at the high strain rate is obtained from the split Hopkinson pressure bar test using disc-type specimens. Experimental results from both quasi-static and dynamic compressive tests are Interpolated to construct the Johnson-Cook model as the constitutive relation that should be applied to simulation of the dynamic behavior of the electrodes. The impact characteristics of a vacuum interrupter are investigated with computer simulations by changing the value of five parameters such as the initial velocity of a movable electrode, the added mass of a movable electrode, the wipe spring constant, initial offset of a wipe spring and the virtual fixed spring constant.

• Korean Journal of Materials Research
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• v.22 no.6
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• pp.280-284
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• 2012

Bismuth antimony telluride (BiSbTe) thermoelectric materials were successfully prepared by a spark plasma sintering process. Crystalline BiSbTe ingots were crushed into small pieces and then attrition milled into fine powders of about 300 nm ~ 2${\mu}m$ size under argon gas. Spark plasma sintering was applied on the BiSbTe powders at 240, 320, and $380^{\circ}C$, respectively, under a pressure of 40 MPa in vacuum. The heating rate was $50^{\circ}C$/min and the holding time at the sintering temperature was 10 min. At all sintering temperatures, high density bulk BiSbTe was successfully obtained. The XRD patterns verify that all samples were well matched with the $Bi_{0.5}Sb_{1.5}Te_{3}$. Seebeck coefficient (S), electric conductivity (${\sigma}$) and thermal conductivity (k) were evaluated in a temperature range of $25{\sim}300^{\circ}C$. The thermoelectric properties of BiSbTe were evaluated by the thermoelectric figure of merit, ZT (ZT = $S^2{\sigma}T$/k). The grain size and electric conductivity of sintered BiSbTe increased as the sintering temperature increased but the thermal conductivity was similar at all sintering temperatures. Grain growth reduced the carrier concentration, because grain growth reduced the grain boundaries, which serve as acceptors. Meanwhile, the carrier mobility was greatly increased and the electric conductivity was also improved. Consequentially, the grains grew with increasing sintering temperature and the figure of merit was improved.

• Progress in Superconductivity
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• v.13 no.2
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• pp.127-132
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• 2011

Many research groups have been manufacturing coated conductor by various processes such as PLD, MOD, and MOCVD, but the methods with production cost suitable for wide and massive application of coated conductor did not develop yet. Spray pyrolysis method adopting ultrasonic atomization was tried as one of the possible option. GdBCO precursor films have been deposited on IBAD substrate by spray pyrolysis method at low temperature and converted to GdBCO by post heat treatment. Ultrasonic atomization was used to generate fine droplets from precursor solution of Gd, Ba, and Cu nitrate dissolved in water. Primary GdBCO films were deposited at $500^{\circ}C$ and oxygen partial pressure of 1 torr. After that, the films were converted at various temperatures and low oxygen partial pressures. C-Axis oriented films were obtained IBAD substrates at conversion temperature of around $870^{\circ}C$ and oxygen partial pressures of 500 mtorr ~ 1 torr in a vacuum. Thick c-axis epitaxial film with the thickness of 0.4 ~ 0.5 ${\mu}m$ was obtained on IBAD substrate. C-axis epitaxial GdBCO films were successfully prepared by ex-situ methods using nitrate precursors on IBAD metal substrate. Converted GdBCO films have very dense microstructures with good grain connectivity. EDS composition analysis of the film showed a number of Cu-rich phase in surface. The precursor solution having high copper concent with the composition of Gd : Ba : Cu = 1 : 2 : 4 showed the better grain connectivity and electrical conductivity.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.12
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• pp.1857-1863
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• 2010

We present the fabrication and characterization of transparent carbon nanotube film (CNF) piezoresistors. CNFs were fabricated by vacuum filtration methods with 65?92% transmittance and patterned on Au-deposited silicon wafer by photolithography and dry etching. The patterned CNFs were transferred onto poly-dimethysiloxane (PDMS) using the weak adhesion property between the silicon wafer and the Au layer. The transferred CNFs were confirmed to be piezoresistors using the equation of concentrated-force-derived resistance change. The gauge factor of the CNFs was measured to range from 10 to 20 as the resistance of the CNFs increased with applied pressure. In polymer microelectromechanical systems, CNF piezoresistors are the promising materials because of their high sensitivity and low-temperature process.