• 한국컴퓨터정보학회논문지
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• 제6권1호
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• pp.74-81
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• 2001

본 논문에서는 ATM 스위치를 사용한 고속 라우터의 구조를 고찰하고 시뮬레이션을 통하여 고속ATM 라우터의 성능을 분석하였다. ATM 스위치를 사용한 고속 ATM 라우터는 플로우(flow)로 정의된 패킷에 대하여 라우터의 처리과정을 생략하고 ATM 스위치를 사용하여 IP 패킷을 처리하기 때문에 라우터의 부하를 줄일 수 있다. 성능 분석을 위한 시뮬레이션에서는 고속 ATM 라우터의 성능 파리미터인 라우팅 시간(routing time: RT), 플로우 테이블 크기 (flow table size : FS), 플로우 리스트 유지시간(flow live time: FT)과 입력 회선 효율을 변화시키면서 라우터의 버퍼 크기를 고찰하였다. 본 논문의 결과는 네트워크를 Upgrade 하거나 ATM 스위치를 이용하여 고속 ATM 라우터를 구현할 때 장비의 적합성을 분석할 수 있는 자료로 사용될 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• ETRI Journal
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• 제41권4호
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• pp.473-482
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• 2019

High availability and reliability have been considered promising requirements for the support of seamless network services such as real-time video streaming, gaming, and virtual and augmented reality. Increased availability can be achieved within a local area network with the use of the virtual router redundancy protocol that utilizes backup routers to provide a backup path in the case of a master router failure. However, the network may still lose a large number of packets during a failover owing to a late failure detections and lazy responses. To achieve an efficient failover, we propose the implementation of fast detection with virtual router redundancy protocol (FDVRRP) in which the backup router quickly detects a link failure and immediately serves as the master router. We implemented the FDVRRP using open neutralized network operating system (OpenN2OS), which is an open-source-based network operating system. Based on the failover performance test of OpenN2OS, we verified that the FDVRRP exhibits a very fast failure detection and a failover with low-overhead packets.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.253-256
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• 1998

In this paper, we discuss the CPU Utilization and bottle neck of the router on campus network. Generally, high CPU utilization does not only makes slow network speed but also frequently network disconnection. The above characteristic is based on the network with one router. In order to solve this problem, we reconstruct network configuration with two routers. Our result shows that CPU utilization of network topology with two router have good performance compared to that with one.

• 정보처리학회논문지A
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• 제8A권2호
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• pp.147-156
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• 2001

A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

• 전기학회논문지P
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• 제66권4호
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• pp.229-235
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• 2017

Until now, a study on a ubiquitous sensor network has been mainly concentrated in the areas of sensor nodes, and as a results, technologies related with sensor node were greatly developed. Despite of many achievements on research and development for a sensor node, a ubiquitous sensor network may failed to establish the actual service environment because variety of restrictions. In order to provide a actual service using a ubiquitous sensor networks applied to many results on research and development for a sensor nodes, a study on a wired/wireless composite router must be carried out. However a study on a wired/wireless composite router is relatively very slow compared with the sensor node. In this study, developed a high-performance router platform supporting IPv6 that can provide high-speed wired/wireless interface and QoS, and it can provide the multimedia service Interlocking the wireless sensor network and the Internet network. To analysis a given network environment and to develop the appropriate hardware and software in accordance with this requirement.

• 대한전자공학회논문지TC
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• 제47권11호
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• pp.97-104
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• 2010

본 논문은 고성능32비트 AES구조를 제시한다. 재배열 구조는 5단 파이프라인을 사용한다. 그 안에 ShiftRows/InvShiftRows 모듈은 4단 파이프라인을 사용하고 MixColumn/InvMixColumn 모듈은 1단 파이프라인을 사용한다. Shift rows와 inverse shift rows 같은 구조를 사용한다. Mix column 과 inverse mix column 도 같은 구조를 사용한다. 그리고 RCON구조를 단순화 하여 사이즈를 줄였다. 제안된 구조는 verilogHDL 을 이용하여 구현 하였다. 이 회로의 처리량은 415Mbits/s 이고 크기는 0.18um CMOS 공정에서 13,764 게이트 이다. 재배열 구조는 무선 네트워크 라우터에서 사용할 수 있다.

• 한국컴퓨터정보학회논문지
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• 제21권5호
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

• 한국통신학회논문지
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• 제28권4B호
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• pp.339-350
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• 2003

인터넷이 급성장하면서 망 사용자들은 대역폭의 증가라는 양적인 측면 외에도 서비스 품질의 개선과 보장이라는 질적인 측면까지 요구하게 되었다. 점점 더 망의 기능성이 강조됨에 따라 망 장비의 성능과 기능도 중요하게 여겨지고 있는데, 특히 에지 라우터는 고성능, 다기능, 유연성이 모두 요구되는 시스템이다. 이러한 특성의 시스템 설계를 위해 최근 고려되고 있는 방법이 네트워크 프로세서를 사용하는 것이다. 본 논문에서는 ASIC의 고성능과 소프트웨어 기반의 유연성을 모두 제공하는 네트워크 프로세서를 사용하여 에지 급의 MPLS 라우터를 개발하고, 그 결과를 기반으로 네트워크 프로세서의 향후 적용가능성을 살펴본다.

• 한국콘텐츠학회논문지
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• 제7권3호
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• pp.50-59
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• 2007

IP 주소 검색은 라우터에서 가장 중요하고 복잡한 기능중 하나이다. 본 논문에서는 고성능 라우터에서 IP 주소 검색의 성능을 향상시키기 위해 LC-trie를 개선하는 기법을 제안한다. TCAM(Ternary Content Addressable Memory)에서 테이블 압축을 위해 이용한 프리픽스 pruning 방법을 LC-trie에 효과적으로 적용한다. 이러한 기법은 메모리 참조 횟수를 감소시키고 검색의 속도를 높일 수 있다. 또한, 실제 사용되는 포워딩 테이블과 트래픽 분포를 사용하여 검색 시간과 메모리 참조 횟수 둥의 관점에서 개선된 기법의 성능을 기존의 LC-trie 기법과 비교 평가한다.