• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.74-81
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• 2001

In this paper. the architecture of a high-speed ATM router using ATM switch is studied and the performance of the high-speed ATM router is analyzed through simulation. The high-speed ATM router using ATM switch is able to reduce the load of router and the processing time of a packet in the router. The size of router buffers has been studied through simulation processes for the analysis of performance capacity in due course of making changes in routing time(RT), which is the performance capacity parameters of high-speed ATM routers, flow table size(FS), flow live time(FT) and input circuit efficiencies. The result of this study can be used as the source material for analyzing the suitability of equipment in upgrading networks and applying high-speed ATM routers by using ATM switches.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• ETRI Journal
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• v.41 no.4
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• pp.473-482
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• 2019

High availability and reliability have been considered promising requirements for the support of seamless network services such as real-time video streaming, gaming, and virtual and augmented reality. Increased availability can be achieved within a local area network with the use of the virtual router redundancy protocol that utilizes backup routers to provide a backup path in the case of a master router failure. However, the network may still lose a large number of packets during a failover owing to a late failure detections and lazy responses. To achieve an efficient failover, we propose the implementation of fast detection with virtual router redundancy protocol (FDVRRP) in which the backup router quickly detects a link failure and immediately serves as the master router. We implemented the FDVRRP using open neutralized network operating system (OpenN2OS), which is an open-source-based network operating system. Based on the failover performance test of OpenN2OS, we verified that the FDVRRP exhibits a very fast failure detection and a failover with low-overhead packets.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.253-256
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• 1998

In this paper, we discuss the CPU Utilization and bottle neck of the router on campus network. Generally, high CPU utilization does not only makes slow network speed but also frequently network disconnection. The above characteristic is based on the network with one router. In order to solve this problem, we reconstruct network configuration with two routers. Our result shows that CPU utilization of network topology with two router have good performance compared to that with one.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.147-156
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• 2001

A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.229-235
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• 2017

Until now, a study on a ubiquitous sensor network has been mainly concentrated in the areas of sensor nodes, and as a results, technologies related with sensor node were greatly developed. Despite of many achievements on research and development for a sensor node, a ubiquitous sensor network may failed to establish the actual service environment because variety of restrictions. In order to provide a actual service using a ubiquitous sensor networks applied to many results on research and development for a sensor nodes, a study on a wired/wireless composite router must be carried out. However a study on a wired/wireless composite router is relatively very slow compared with the sensor node. In this study, developed a high-performance router platform supporting IPv6 that can provide high-speed wired/wireless interface and QoS, and it can provide the multimedia service Interlocking the wireless sensor network and the Internet network. To analysis a given network environment and to develop the appropriate hardware and software in accordance with this requirement.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.97-104
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• 2010

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

• Journal of the Korea Society of Computer and Information
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• v.21 no.5
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• pp.49-56
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• 2016

Increasing Internet traffic and forwarding table size need high performance IP address lookup engine which is a crucial function of routers. For finding the longest matching prefix, trie-based or its variant schemes have been widely researched in software-based IP lookup. As a software router, we enhance the IP address lookup engine using GPU which is a device widely used in high performance applications. We propose a data structure for multibit trie to exploit GPU hardware efficiently. Also, we devise a novel scheme that the root subtrie is loaded on Shared Memory which is specialized for fast access in GPU. Since the root subtrie is accessed on every IP address lookup, its fast access improves the lookup performance. By means of the performance evaluation, our implemented GPU-based lookup engine shows 17~23 times better performance than CPU-based engine. Also, the fast access technique for the root subtrie gives 10% more improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.339-350
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• 2003

The demands of network users emphasize the improvement and guarantee of service quality as well as the increment of bandwidth. As a result, high performance and additional new functions are important features to build network equipments, especially and edge router. For this structure, network processors with high performance and flexibility are considered as a main part of a packet forwarding module. In this paper, we design and edge MPLS router with a network processor, which supports high performance and multi-functionalities and examine its advantage and limitation.

• The Journal of the Korea Contents Association
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• v.7 no.3
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• pp.50-59
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• 2007

IP address lookup is one of the most important and complex functions in the router. In this paper, we propose an improved technique of LC-trie to increase the performance of IP address lookup in the high performance router. We effectively apply the prefix pruning method, which is used for the compression of the forwarding table in TCAM((Ternary Content Addressable Memory), to the LC-trie. This technique can decrease the number of memory accesses and upgrade the lookup speed. Moreover, through the real forwarding table and the real traffic distribution, we evaluate the performance of our scheme in terms of the lookup time and the number of memory access, comparing with that of the previous LC-trie.