• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.293.1-293.1
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• 2016

Various materials including conductive, dielectric, and semi-conductive materials, constitute suitable candidates for printed electronics. Metal nanoparticles (e.g. Ag, Cu, Ni, Au) are typically used in conductive ink. However, easily oxidized metals, such as Cu, must be processed at low temperatures and as such, photonic sintering has gained significant attention as a new low-temperature processing method. This method is based on the principle of selective heating of a strongly absorbent film, without light-source-induced damage to the transparent substrate. However, Cu nanoparticles used in inks are susceptible to the growth of a native copper-oxide layer on their surface. Copper-oxide-nanoparticle ink subjected to a reduction mechanism has therefore been introduced in an attempt to achieve long-term stability and reliability. In this work, a flash-light sintering process was used for the reduction of an inkjet-printed Cu(II)O thin film to a Cu film. Using a photographic lighting instrument, the intensity of the light (or intense pulse light) was controlled by the charged power (Ws). The resulting changes in the structure, as well as the optical and electrical properties of the light-irradiated Cu(II)O films, were investigated. A Cu thin film was obtained from Cu(II)O via photo-thermal reduction at 2500 Ws. More importantly, at one shot of 3000 Ws, a low sheet resistance value ($0.2527{\Omega}/sq.$) and a high resistivity (${\sim}5.05-6.32{\times}10^{-8}{\Omega}m$), which was ~3.0-3.8 times that of bulk Cu was achieved for the ~200-250-nm-thick film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.10-10
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• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.129-129
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• 2016

Graphene, as a single layer of $sp^2$-bonded carbon atoms packed into a 2D honeycomb crystal lattice, has attracted much attention due to its outstanding properties. In order to synthesize high quality graphene, transition metals, such as nickel and copper, have been widely employed as catalysts, which needs transfer to desired substrates for various applications. However, the transfer steps are not only complicated but also inevitably induce defects, impurities, wrinkles, and cracks of graphene. Furthermore, the direct synthesis of graphene on dielectric surfaces has still been a premature field for practical applications. Therefore, cost effective and concise methods for transfer-free graphene are essentially required for commercialization. Here, we report a facile transfer-free graphene synthesis method through nickel and carbon co-deposited layer. In order to fabricate 100 nm thick NiC layer on the top of $SiO_2/Si$ substrates, DC reactive magnetron sputtering was performed at a gas pressure of 2 mTorr with various Ar : $CH_4$ gas flow ratio and the 200 W DC input power was applied to a Ni target at room temperature. Then, the sample was annealed under 200 sccm Ar flow and pressure of 1 Torr at $1000^{\circ}C$ for 4 min employing a rapid thermal annealing (RTA) equipment. During the RTA process, the carbon atoms diffused through the NiC layer and deposited on both sides of the NiC layer to form graphene upon cooling. The remained NiC layer was removed by using a 0.5 M $FeCl_3$ aqueous solution, and graphene was then directly obtained on $SiO_2/Si$ without any transfer process. In order to confirm the quality of resulted graphene layer, Raman spectroscopy was implemented. Raman mapping revealed that the resulted graphene was at high quality with low degree of $sp^3$-type structural defects. Additionally, sheet resistance and transmittance of the produced graphene were analyzed by a four-point probe method and UV-vis spectroscopy, respectively. This facile non-transfer process would consequently facilitate the future graphene research and industrial applications.