• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.4
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• pp.169-174
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• 2002

This paper presents a high-resolution capactive microaccelerometer using branched finger electrodes with high-amplitude sense voltage. From the fabricated microacceleromcter, the total noise is obtained as 9 $\mu\textrm{g}$/√Hz at the sense voltage of 16.5V, while the conventional microaccelerometers have shown the noire level of 25~800 $\mu\textrm{g}$/√Hz. We reduce the mechanical noise level of the microaccelerometer by increasing the proof-class based on deep RIE process of an SOI wafer. We reduce the electrical noise level by increasing the amplitude of AC sense voltage. The nonlinearity problem caused by the high-amplitude sense volage has been solved by a new electrode design of branched finger type, resulting in self force-balancing effects for the enhanced linearity and bandwidth. The fabricated microaccelerometer shows the electrical noise of 2.4 $\mu\textrm{g}$/√Hz at the sense voltage of 16.5V, which is an order of magnitude reduction of the electrical noise of 24.3 $\mu\textrm{g}$/√Hz measured at 0.9V. For the sense voltage higher than 2V, the electrical noise of the microaccelerometer is lower than the voltage-independent mechanical noise of 11 $\mu\textrm{g}$/√Hz. Total noise, composed of the electrical noise and the mechanical noire, has been measured as 9 $\mu\textrm{g}$/√Hz at the sense voltage of 16.5V, which is 31% of the total noise of 28.6 $\mu\textrm{g}$/√Hz at the sense voltage 0.9V. The self force-balancing effect in the blanched finger electrodes increases the stiffness of the microaccelerometer from 1.1N/m to 1.61N/m as the sense voltage increases from 0V to 17.8V, thereby generating additional stiffness at the rate of 0.0016$\pm$0.0008 N/m/V$^2$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.1
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• pp.1-10
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• 2004

This paper presents a navigation garde capacitive microaccelerometer, whose low-noise high-resolution detection capability is achieved by a new electrode design based on a high-amplitude anti-phase sense voltage. We reduce the mechanical noise of the microaccelerometer to the level of 5.5$\mu\textrm{g}$/(equation omitted) by increasing the proof-mass based on deep RIE process of an SOI wafer. We reduce the electrical noise as low as 0.6$\mu\textrm{g}$/(equation omitted) by using an anti-phase high-amplitude square-wave sense voltage of 19V. The nonlinearity problem caused by the high-amplitude sense voltage is solved by a new electrode design of branched finger type. Combined use of the branched finger electrode and high-amplitude sense voltage generates self force-balancing effects, resulting in an 140％ increase of the bandwidth from 726㎐ to 1,734㎐. For a fixed sense voltage of 10V, the total noise is measured as 2.6$\mu\textrm{g}$/(equation omitted) at the air pressure of 3.9torr, which is the 51％ of the total noise of 5.1$\mu\textrm{g}$/(equation omitted) at the atmospheric pressure. From the excitation test using 1g, 10㎐ sinusoidal acceleration, the signal-to-noise ratio of the fabricated microaccelerometer is measured as 105㏈, which is equivalent to the noise level of 5.7$\mu\textrm{g}$/(equation omitted). The sensitivity and linearity of the branched finger capacitive microaccelerometer are measured as 0.638V/g and 0.044％, respectively.

• Proceedings of the KSME Conference
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• 2001.06c
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• pp.53-58
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• 2001

This paper presents a high resolution capacitive microaccelerometer for applications to personal information systems. We reduce the mechanical noise level of the microaccelerometer by increasing the proof-mass based on deep RIE process. We reduce the electrical noise level by increasing the amplitude of an AC sense voltage. The high sense voltage is obtained by DC-to-DC voltage multiplier. In order to solve the nonlinearity problem caused by the high sense voltage, we modify the conventional comb electrode of straight finger type into that of branched finger type, resulting in self force-balancing effects for enhanced detection linearity. The proposed branched finger capacitive microaccelerometer was fabricated by the deep RIE process of an SOI wafer. The fabricated microaccelerometer reduces the electrical noise at the level of $2.4{\mu}g/\sqrt{Hz}$ for the sense voltage of l6.5V, which is 10.1 times smaller than the electrical noise level of $24.3{\mu}g/\sqrt{Hz}$ at 0.9V. For the sense voltage higher than 2V, the electrical noise level of the microaccelerometer became smaller than the constant mechanical noise level of $11{\mu}g/\sqrt{Hz}$. Total noise level, including the electrical noise and the mechanical noise, has been measured as $9{\mu}g/\sqrt{Hz}$ for the sense voltage of 16.5V, which is 3.2 times smaller than the total noise of $28.6{\mu}g/\sqrt{Hz}$ for the sense voltage of 0.9V. The self force-balancing effect results in the increased stiffness of 1.98 N/m at the sense voltage of 17.8V, compared to the stiffness of 1.35 N/m at 0V, thereby generating the additional stiffness at the rate of $0.002N/m/V^{2}$.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.