• 한국컴퓨터정보학회논문지
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• 제18권7호
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• pp.111-123
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• 2013

소프트웨어의 취약성을 검증하기 위하여 소프트웨어의 구조를 유추하여 유추된 구조를 활용하여 테스트하는 방법이 주목받고 있다. 이와 같은 방법을 사용하기 위해서 효과적인 소프트웨어의 구조 유추 방법이 요구된다. 많이 사용되는 DFG(Data Flow Graph), CFG(Control Flow Graph) 이나 CFA(Control Flow Automata)와 같은 그래프나 트리 방식은 소프트웨어 모델을 구조적으로 표현하지 못하는 단점을 가진다. 본 논문에서는 이러한 단점을 극복할 수 있는 방법을 제시한다. 제시된 방법은 바이너리 코드에 다양한 입력데이터 들을 부여하여 입력데이터별 CFG를 생성하고, 생성된 CFG들이 구조적으로 표현될 수 있도록 계층적 제어 흐름 그래프(Hierarchical Control Flow Graph, HCFG)를 작성한다. 또한 제안하는 HCFG을 생성하는데 요구되는 그래프의 구성요소와 점진적 그래프 생성 알고리듬도 제시한다. 제안한 방법론을 공개된 SMTP(Simple Mail Transfer Protocol) 서버 프로그램에 적용시켜 소프트웨어의 모델을 작성하는 실험을 수행하고, 생성된 모델과 실제 소프트웨어 구조를 비교 분석한다.

• 한국정보과학회논문지:시스템및이론
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• 제29권12호
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• pp.655-664
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• 2002

데이타 병렬 모델은 대규모 병렬성을 용이하게 얻을 수 있는 장점이 있지만, 데이타 분산으로 인한 통신 지연시간은 상당한 부담이 된다. 본 논문에서는 데이타 병렬 프로그램에 내재되어 있는 태스크 병렬성을 추출하여 이러한 통신 지연시간을 감추는데 이용할 수 있음을 보인다. 기존의 태스크 병렬성 추출은 데이타 병렬성을 고려하지 않았지만, 여기서는 데이타 병렬성을 그대로 유지하면서 태스크 병렬성을 활용하는 방법에 대해 설명한다. 데이타 병렬 루프를 포함할 수 있는 다수의 태스크 스레드들로 구성된 다중스레드 프로그램을 표현하기 위해 본 논문에서는 PCFG(Parallel Control Flow Graph)라는 표현 형태를 제안한다. PCFG는 단일 스레드인 원시 데이타 병렬 프로그램으로부터 HDG(Hierarchical Dependence Graph)를 통해 생성될 수 있으며, 또한 PCFG로부터 다중스레드 코드를 쉽게 생성할 수 있다.

• 정보처리학회논문지D
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• 제13D권1호
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• pp.117-124
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• 2006

UML(Unified Modeling Language)은 객체지향 모델링을 위한 언어이다 UML에 포함되어 있는 AD(Activity Diagram; 활동 다이어그램)는 워크플로우 시스템의 모델링에 적합하지만 수행 과정의 평가가 수학적이지 못하므로 수행 과정을 직관적으로 파악해야 하는 단점이 있다. 그러나 EMFG(Extended Mark Flow Graph)는 이산적인 시스템의 모델링에 적합할 뿐 아니라 수행 과정을 수학적으로 평가할 수 있다. 따라서 본 연구에서는 EMFG를 사용하여 모델링된 AD의 수행 동작을 평가하려고 한다. 우선 AD를 EMFG로 변환하는 방법에 대하여 제안하고, 변환된 EMFG의 수행을 평가함으로써 모델링된 AD의 수행완료 가능성을 평가한다. 그리고 컴퓨터 시뮬레이션을 통하여 이를 입증한다. 제안한 알고리듬은 대규모 워크플로우 시스템을 모델링한 AD의 수행완료 가능성도 쉽게 평가할 수 있는 장점이 있다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권8호
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• pp.2101-2123
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• 2023

Recent studies have shown that the neural network-based binary code similarity detection technology performs well in vulnerability mining, plagiarism detection, and malicious code analysis. However, existing cross-architecture methods still suffer from insufficient feature characterization and low discrimination accuracy. To address these issues, this paper proposes a cross-architecture binary function similarity detection method based on composite feature model (SDCFM). Firstly, the binary function is converted into vector representation according to the proposed composite feature model, which is composed of instruction statistical features, control flow graph structural features, and application program interface calling behavioral features. Then, the composite features are embedded by the proposed hierarchical embedding network based on a graph neural network. In which, the block-level features and the function-level features are processed separately and finally fused into the embedding. In addition, to make the trained model more accurate and stable, our method utilizes the embeddings of predecessor nodes to modify the node embedding in the iterative updating process of the graph neural network. To assess the effectiveness of composite feature model, we contrast SDCFM with the state of art method on benchmark datasets. The experimental results show that SDCFM has good performance both on the area under the curve in the binary function similarity detection task and the vulnerable candidate function ranking in vulnerability search task.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 춘계학술대회 논문집
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• pp.457-462
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• 1995

This paper describes diagnosis strategy of the Flexible Multiple Fault Diagnosis Module for forecasting faults in system and deciding current machine state form sensor information. Most studydeal with diagnosis control stategy about single fault in a system, this studies deal with multiple fault diagnosis. This strategy is consist of diagnosis control module such as backward tracking expert system shell, various neural network, numerical model to predict machine state and communication module for information exchange and cooperate between each model. This models are used to describe structure, function and behavior of subsystem, complex component and total system. Hierarchical structure is very efficient to represent structural, functional and behavioral knowledge. FT(Fault Tree). ST(Symptom Tree), FCD(Fault Consequence Diagrapy), SGM(State Graph Model) and FFM(Functional Flow Model) are used to represent hierachical structure. In this study, IA(Intelligent Agent) concept is introduced to match FT component and event symbol in diagnosed system and to transfer message between each event process. Proposed diagnosis control module is made of IPC(Inter Process Communication) method under UNIX operating system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.589-594
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• 1991

Group Technology (GT) is a technique for identifying and bringing together related or similar components in a production process in order to take advantage of their similarities by making use of, for example, the inherent economies of flow production methods. The process of identification, from large variety and total of components, of the part families requiring similar manufacturing operations and forming the associated groups of machines is referred as 'machine-component grouping'. First part of this paper is devoted to describing a hierarchical divisive algorithm based on graph theory to find the natural part families. The objective is to form components into part families such that the degree of inter-relations is high among components within the same part family and low between components of different part families. Second part of this paper focuses on establishing cell design procedures. The aim is to create cells in which the most expensive and important machines-called key machine - have a reasonably high utilization and the machines should be allocated to minimize the intercell movement of machine loads. To fulfil the above objectives, 0-1 integer programming model is developed and the solution procedures are found. Next an attempt is made to test the feasibility of the proposed method. Several different problems appearing in the literature are chosen and the results air briefly showed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.