• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.111-123
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• 2013

To verify software vulnerability, the method of conjecturing software structure and then testing the software based on the conjectured structure has been highlighted. To utilize the method, an efficient way to conjecture software structure is required. The popular graph and tree methods such as DFG(Data Flow Graph), CFG(Control Flow Graph) and CFA(Control Flow Automata) have a serious drawback. That is, they cannot express software in a hierarchical fashion. In this paper, we propose a method to overcome the drawback. The proposed method applies various input data to a binary code, generate CFG's based on the code output and construct a HCFG (Hierarchical Control Flow Graph) to express the generated CFG's in a hierarchical structure. The components required for HCFG and progressive algorithm to construct HCFG are also proposed. The proposed method is verified through constructing the software architecture of an open SMTP(Simple Mail Transfer Protocol) server program. The structure generated by the proposed method and the real program structure are compared and analyzed.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.655-664
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• 2002

In many data-parallel applications massive parallelism can be easily extracted through data distribution. But it often causes very long communication latency. This paper shows that task parallelism, which is extracted from data-parallel programs, can be exploited to hide such communication latency Unlike the most previous researches over exploitation of task parallelism which has not been considered together with data parallelism, this paper describes exploitation of task parallelism in the context of data parallelism. PCFG(Parallel Control Flow Graph) is proposed to represent a multithreaded program consisting of a few task threads each of which can include a few data-parallel loops. It is also described how a PCFG is constructed from a source data-parallel program through HDG(Hierarchical Dependence Graph) and how the multithreaded program can be constructed from the PCFG.

• The KIPS Transactions:PartD
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• v.13D no.1 s.104
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• pp.117-124
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• 2006

Hardware and software codesign framework called PeaCE(Ptolemy extension as a Codesign Environment) was developed. It allows to express both data flow and control flow which is described as fFSM which extends traditional finite state machine. While the fFSM model provides lots of syntactic constructs for describing control flow, it has a lack of their formality and then difficulties in verifying the specification. In order to define the formal semantics of the fFSM, in this paper, firstly the hierarchical structure in the model is flattened and then the step semantics is defined. As a result, some important bugs such as race condition, ambiguous transition, and circulartransition can be formally detected in the model.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.8
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• pp.2101-2123
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• 2023

Recent studies have shown that the neural network-based binary code similarity detection technology performs well in vulnerability mining, plagiarism detection, and malicious code analysis. However, existing cross-architecture methods still suffer from insufficient feature characterization and low discrimination accuracy. To address these issues, this paper proposes a cross-architecture binary function similarity detection method based on composite feature model (SDCFM). Firstly, the binary function is converted into vector representation according to the proposed composite feature model, which is composed of instruction statistical features, control flow graph structural features, and application program interface calling behavioral features. Then, the composite features are embedded by the proposed hierarchical embedding network based on a graph neural network. In which, the block-level features and the function-level features are processed separately and finally fused into the embedding. In addition, to make the trained model more accurate and stable, our method utilizes the embeddings of predecessor nodes to modify the node embedding in the iterative updating process of the graph neural network. To assess the effectiveness of composite feature model, we contrast SDCFM with the state of art method on benchmark datasets. The experimental results show that SDCFM has good performance both on the area under the curve in the binary function similarity detection task and the vulnerable candidate function ranking in vulnerability search task.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.04b
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• pp.457-462
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• 1995

This paper describes diagnosis strategy of the Flexible Multiple Fault Diagnosis Module for forecasting faults in system and deciding current machine state form sensor information. Most studydeal with diagnosis control stategy about single fault in a system, this studies deal with multiple fault diagnosis. This strategy is consist of diagnosis control module such as backward tracking expert system shell, various neural network, numerical model to predict machine state and communication module for information exchange and cooperate between each model. This models are used to describe structure, function and behavior of subsystem, complex component and total system. Hierarchical structure is very efficient to represent structural, functional and behavioral knowledge. FT(Fault Tree). ST(Symptom Tree), FCD(Fault Consequence Diagrapy), SGM(State Graph Model) and FFM(Functional Flow Model) are used to represent hierachical structure. In this study, IA(Intelligent Agent) concept is introduced to match FT component and event symbol in diagnosed system and to transfer message between each event process. Proposed diagnosis control module is made of IPC(Inter Process Communication) method under UNIX operating system.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.589-594
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• 1991

Group Technology (GT) is a technique for identifying and bringing together related or similar components in a production process in order to take advantage of their similarities by making use of, for example, the inherent economies of flow production methods. The process of identification, from large variety and total of components, of the part families requiring similar manufacturing operations and forming the associated groups of machines is referred as 'machine-component grouping'. First part of this paper is devoted to describing a hierarchical divisive algorithm based on graph theory to find the natural part families. The objective is to form components into part families such that the degree of inter-relations is high among components within the same part family and low between components of different part families. Second part of this paper focuses on establishing cell design procedures. The aim is to create cells in which the most expensive and important machines-called key machine - have a reasonably high utilization and the machines should be allocated to minimize the intercell movement of machine loads. To fulfil the above objectives, 0-1 integer programming model is developed and the solution procedures are found. Next an attempt is made to test the feasibility of the proposed method. Several different problems appearing in the literature are chosen and the results air briefly showed.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.815-818
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• 1998

Hardware formal verification involves the use of analytical techniques to prove that the implementation of a system confroms to the specification. The specification could be a set of properties that the system must have or it could be an alternative representation of the system behavior. We can represent our behavioral specification to be written in VHDL coding. In this paper, we proposed a new hardware design verification method. For theis method, we assumed that a verification pattern already exists and try to make an algorithm to find a place where a design error occurred. This method uses an hierarchical approach by making control flow graph(CFG) hierarchically. From the simulation, this method was turned out to be very effective that all the assumed design errors could be detected.