• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.948-950
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• 2002

IPSec authentication provides support for data integrity and authentication of IP packets. Authentication is based on the use of a message authentication code(MAC). Hash function algorithm is used to produce MAC , which is referred to HMAC. In this paper, we propose a cryptographic accelerator using FPGA implementations. The accelator consists of a hash function mechanism based on MD5 algorithm, and a public-key generator based on a Elliptiv Curve algorithm with small scale of circuits. The accelator provides a messsage authentification as well as a digital signature. Implementation results show the proposed cryptographic accelerator can be applied to IPSec authentications.

• Journal of Korea Multimedia Society
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• v.11 no.6
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• pp.845-851
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• 2008

The ID/password method is the most classical method among authentication techniques on the internet, and is performed more easily and successfully than other methods. However, it is a vulnerable method against attacks such as eavesdropping or replay attack. To overcome this problem, OTP technique is used. The most popular OTP is HOTP algorithm, which is based on one-way hash function SHA-1. As recent researches show the weakness of the hash function, we need a new algorithm to replace HOTP. In this paper we propose a new OTP algorithm using the MAC(Message Authentication Code) based on AES. We also show that the new OTP outperforms HOTP experimentally.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.13-21
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• 2010

One of the most distinguished features of the DHP association rules mining algorithm is that it counts the support of hash key combinations composed of k items at phase k-1, and uses the counted support for pruning candidate large itemsets to improve performance. At this time, it is desirable for each hash key combination to have a separate count variable, where it is impossible to allocate the variables owing to memory shortage. So, the algorithm uses a direct hashing mechanism in which several hash key combinations conflict and are counted in a same hash bucket. But the direct hashing mechanism is not efficient because the distribution of hash key combinations is unvalanced by the characteristics sourced from the mining process. This paper proposes a mapped perfect hashing function which maps the region of hash key combinations into a continuous integer space for phase 3 and maximizes the efficiency of direct hashing mechanism. The results of a performance test experimented on 42 test data sets shows that the average performance improvement of the proposed hashing mechanism is 7.3% compared to the existing method, and the highest performance improvement is 16.9%. Also, it shows that the proposed method is more efficient in case the length of transactions or large itemsets are long or the number of total items is large.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.10
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• pp.61-67
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• 2016

With the current high distribution rate of smart devices and the recent development of computing technology, user interest in multimedia, such as photos, videos, and so on, has rapidly increased, which is a departure from the simple pattern of information retrieval. Because of these increasing interests, image processing techniques, which generate and process images for diverse applications, are being developed. In entertainment recently, there are some techniques that present a celebrity's image as a mosaic comprising many small images. In addition, studies into the mosaic technique are actively conducted. However, conventional mosaic techniques result in a long processing time as the number of database images increases, because they compare the images in the databases sequentially. Therefore, to increase search efficiency, this paper proposes an algorithm to generate a mosaic image using a discrete cosine transform (DCT) hash. The proposed photo mosaic-generation algorithm is composed of database creation and mosaic image generation. In database creation, it first segments images into blocks with a predefined size. And then, it computes and stores a DCT hash set for each segmented block. In mosaic generation, it efficiently searches for the most similar blocks in the database via DCT hash for every block of the input image, and then it generates the final mosaic. With diverse experimental results, the proposed photo mosaic-creation algorithm can effectively generate a mosaic, regardless of the various types of images and sizes.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1031-1040
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• 2010

Hash join is one of the core algorithms in databases management systems. If a hash join cannot complete in one-pass because the available memory is insufficient (i.e., hash table overflow), however, it may incur a few sequential writes and excessive random reads. With harddisk as the tempoary storage for hash joins, the I/O time would be dominated by slow random reads in its probing phase. Meanwhile, flash memory based SSDs (flash SSDs) are becoming popular, and we will witness in the foreseeable future that flash SSDs replace harddisks in enterprise databases. In contrast to harddisk, flash SSD without any mechanical component has fast latency in random reads, and thus it can boost hash join performance. In this paper, we investigate several important and practical issues when flash SSD is used as tempoary storage for hash join. First, we reveal the va patterns of hash join in detail and explain why flash SSD can outperform harddisk by more than an order of magnitude. Second, we present and analyze the impact of cluster size (i.e., va unit in hash join) on performance. Finally, we emperically demonstrate that, while a commerical query optimizer is error-prone in predicting the execution time with harddisk as temporary storage, it can precisely estimate the execution time with flash SSD. In summary, we show that, when used as temporary storage for hash join, flash SSD will provide more reliable cost estimation as well as fast performance.

• Review of KIISC
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• v.6 no.1
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• pp.79-88
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• 1996

작년 6월호에 ISO/IEC 10118의 제 1 부인 개론이 소개되었고 이번호에는 바로 표준이 된 제 2 부를 소개한다. 이 과제는 1990년에 CD(Committee Draft), 1992년에 DIS(Draft IS)가 되었고, 1994년에 IS(International Standard)가 되었으며 1998년에 1차 검토가 있을 예정이다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.913-916
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• 2009

This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

• Journal of information and communication convergence engineering
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• v.5 no.3
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• pp.254-258
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• 2007

Recently, ubiquitous computing in being actively researched and one of the main technology in ubiquitous computing environments is recognized as RFID system. The RFID system has much benefits but simultaneously has some problems such as user's privacy violation. In this paper, in order to improve the survivability of its nodes, it should build available simulation surrounding sensor nodes. Also, In the proposed cryptosystems we use a new hash function for user authentication and a stream cipher based on LFSR(Linear Feedback Shift Register) for message encryption and decryption. Moreover, each algorithm is programmed with C language and simulated on IBM-PC system and we analyze the randomness properties of the proposed algorithms by using statistical tests.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.194-196
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• 2017

본 설계에서는 임의의 길이의 메시지를 256-비트의 해시 코드로 압축하는 해시 알고리듬인 SHA-256(Secure Hash Algorithm-256) 해시함수를 경량화 구현 설계 하였다. 미국 표준 기술연구소 NIST에서 발표한 표준문서 FIPS 180-4에 정의16된 32-비트의 데이터 패스를 16-비트로 설계하여 경량화 구현하였다. Verilog HDL로 설계된 SHA-256 해시함수는 Xilinx ISim를 사용하여 시뮬레이션 검증을 하였다. CMOS 표준 셀 라이브러리로 합성한 결과 100MHz 동작주파수에서 18,192 GE로 구현되었으며, 192MHz의 최대 동작주파수를 갖는다.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11c
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• pp.1367-1370
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• 2003

본 논문에서는 인덱스가 존재하지 않는 두 개의 입력 릴레이션에 대해서도 최적의 조인 연산을 수행할 수 있는 공간 해쉬 조인 알고리즘을 제안한다. 인덱스가 존재하지 않는 릴레이션의 처리에 사용하는 기존의 공간 해쉬 조인(SHJ: Spatial Hash Join)과 Scalable Sweeping-Rased Spatial Join(SSSJ) 알고리즘을 결합하여 SHJ 알고리즘의 단점으로 지적되고 있는 편향된(skewed) 데이터에 대한 조인 연산의 성능저하 문제를 개선한 수 있는 Spatial Hash Strip Join(SHSJ) 알고리즘을 제안한다. SHJ에서 편향된 데이터의 경우 해쉬 버킷의 오버플로우 처리를 위해 버킷 재분할 방법을 사용하고 있는데 반하여 본 논문에서 제안한 SHSJ 알괴리즘에서는 버킷의 재분할 처리 대신에 버킷에 데이터를 삽입하고, 조인 연산과정에서 오버플로우가 발생한 버킷에 대하여 SSSJ 알고리즘을 사용함으로써 편향된 입력 릴레이션의 처리 성능을 제고시킬 수 있도록 한다.