• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.621-624
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• 2003

In this paper, a novel multilevel inverter using DC-Link voltage combination is presented to reduce the harmonics of output voltage without the output filter inductor. The proposed multilevel inverter can generate 27-level output voltage. It employs three H-bridge cells which consist of single phase full-bridge inverter module. As well as, it can make continuous output voltage level employing the properly three DC-Link voltage ratio. The validity of the proposed inverter is verified through the experimental result using a prototype which can generate a 110[Vac], 60[Hz] output voltage from 12[Vdc], 36[vdc], and 108[Vdc] input voltages

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.3
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• pp.125-132
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• 2002

This paper presents a single-phase 3-level PWM inverter to alleviate the harmonic components of output voltage and current under the conditions of identical supply DC voltage and switching frequency to the conventional inverter. Operational principles and analysis are performed, and the switching functions are derived. Deadbeat controller is also designed and implemented for the inverter to keep the output voltage being sinusoidal and to have the high dynamic performances even in the cases of load variations and the partial magnetization of filter inductor. The validity of proposed inverter is proved from the simulated and experimented results.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.105-107
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• 2018

This paper presents a new hybrid multilevel converter topology, which consists of a combination of the series connected switched capacitor units with boost ability, and an H-bridge with T-type bidirectional switches. The proposed converter boosts the input voltage without any bulky inductors, and has the small number of components, which can make the size and cost of a power converter greatly reduced. The output filter size and harmonics are also reduced by the high quality multilevel output. In addition, there is no need for complicated methods to balance the capacitor voltage. Simulation and experimental results with a nine-level converter system are presented to validate the proposed topology and modulation method.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.2
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• pp.80-88
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• 1988

As a method to improve harmonics in the voltage source PWM inverter, 5 level stair case wave method is used. The complementary transistor inverter (CTI) bridge circuit has this characteristics. This circuit required synchronous type 3 level PWM signal. In this paper, the 3 phase PWM digital signals within about 10 modulation error of the natural sampling was caculated, and a ROM table out of it for the digital signal of the control system was made. According to this table, the digital control method was proposed, and DTI circuit operated by this method was reviewed. It was confirmed to make V/F control possible by the select modulation ratio to the frequency.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.368-370
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• 1995

A new three-level push-pull type quantum series resonant rectifier for the power factor correction is proposed. The proposed single phase rectifier enables a zero-current switching operation of all the power devices allowing the circuit to operate at high switching frequencies and high power levels. With the proposed control technique, an unity power factor and greatly reduced line current harmonics can be obtained.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.738-750
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• 2017

In this paper, carrier-based pulse width modulation (CBPWM), space vector PWM (SVPWM) and reduced switching losses PWM (RSLPWM) for the three-level neutral point clamped (NPC) inverter are introduced. In the case of the neutral point (NP) potential (NPP) offset, an asymmetric disposition PWM (ASPDPWM) strategy is proposed, which can output PWM sequences correctly and suppress the lower order harmonics of the inverter effectively. An NPP balance strategy based on carrier based PWM (CBPWM) is analyzed. A hybrid modulation strategy combining RSLPWM and the NPP balance based on CBPWM is proposed, and hysteresis control is adopted to switch between the two modulation strategies. An experimental prototype of the three-level NPC inverter is built. The effectiveness of the hybrid modulation is verified with a resistance-inductance load and a permanent magnetic synchronous motor (PMSM) load, respectively. The experimental results show that reduced switching losses and an acceptable NPP can be effectively achieved in the hybrid modulation strategy.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.2
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• pp.68-74
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• 2004

This paper presents a novel hybrid multilevel inverter using DC-Link voltage combination in order to improve the waveshape of output voltage and reduce harmonics. The proposed multilevel inverter can generate an 11-level output voltage. It employs three H-bridge cell, which consists of single phase full-bridge inverter module. Among them, two modules are used for level generation, and one module performs PWM switching. Nine levels are synthesised by the level inverter, and two levels are added to output by the PWM inverter. As a result, it generates an 11-level. The operational principles are explained in depth, and the validity of the proposed system is verified through the PSpice simulation and experimental results based on a prototype.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1571-1577
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• 1994

This paper is designed and implemented mixer of 12GHz/14GHz as up-conversion. Observation that harmonics and intermodulation power level varied by two signal power level and bias obtained operation points of mixer. Finally, optimum operation points shows that $P_{RF}$(radio signal frequency power level). $P_{LO}$(local oscillation power level) is below -30[dBm], -2[dBm] respectively. Simultaneously $V_{DS}$ is 2.7[V]and $V_{GS}$ is -0.2[V].

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.711-721
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• 2018

This paper presents a single-phase asymmetric half-bridge cascaded multilevel inverter based series active power filter (SAPF) for harmonic voltage compensation. The effect of level number on performance of the proposed SAPF is examined in terms of total harmonic distortion (THD) and system efficiency. Besides, the relationship between the level number and the number of switching device are compared with the other multilevel inverter topologies used in APF applications. The paper is also aimed to demonstrate the capability of the SAPF for compensating harmonic voltages alone, without using a passive power filter (PPF). To obtain the required output voltage, a new switching algorithm is developed. The proposed SAPF with levels of 7, 15 and 31 is used in both simulation and experimental studies and the harmonic voltages of the load connected to the point of common coupling (PCC) is compensated under two different loading conditions. Furthermore, very high system efficiency values such as 98.74% and 96.84% are measured in the experimental studies and all THD values are brought into compliance with the IEEE-519 Standard. As a result, by increasing the level number of the inverter, lower THD values can be obtained even under high harmonic distortion levels while system efficiency almost remains the same.