• Title/Summary/Keyword: Harmonics Elimination

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Harmonic Analysis and Filter Design on Distribution System using SuperHarm (배전계통에서의 SuperHarm을 이용한 고조파.분석 및 필터 설계)

  • 이종포;김철환
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.14 no.5
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    • pp.36-42
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    • 2000
  • The increasing application of power electronic equipment 'especially (ASDs: adjustable speed drives)] on distribution systems has led to a growing concern for harmonic distortion and the resulting impacts on system equipment and operations. Therefore, harmonic studies have become an important aspect of power system analysis and design in recently years. Computer simulations which is related harmonic are used to quantify the distortion in voltage waveforms in a power system. Many digital computer programs are available for harmonic analysis. In frequency spectrum analysis, Simulation using SuperHarm program is superior to simulation using others. Therefore, Computer simulation using SuperHarm program is one of the effective ways to assess the harmonic effects of ASDs. The purpose of this study is to calculate the quantity of harmonic voltage by varying the ASD side load and to design the optimal harmonic filter for the elimination of harmonics.

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Design and Fabrication of Low Loss, High Power SP6T Switch Chips for Quad-Band Applications Using pHEMT Process (pHEMT 공정을 이용한 저손실, 고전력 4중 대역용 SP6T 스위치 칩의 설계 및 제작)

  • Kwon, Tae-Min;Park, Yong-Min;Kim, Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.6
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    • pp.584-597
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    • 2011
  • In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.