• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.1-6
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• 2011

In this paper, an 1.5Gbit/s wireless data transmission system using the carrier frequency of 300 GHz band was implemented. The RF front-end was composed of schottky diode sub-harmonic mixer, frequency tripler, and horn antennas for transmitter and receiver, respectively. The LO frequencies of sub-harmonic mixer are 150GHz for transmit chain and 156GHz for receive chain. The ASK(Amplitude Shift Keying) modulation was used in the transmitter and the envelope detection method was used in the heterodyne receiver. The conversion loss of sub-harmonic mixer and implementation system loss were measured to be 9.8dB and 1.2dB, respectively. The 1.5Gbit/s video signal with HD-SDI format was transmitted over wireless distance of 40cm without optical lens(4.2m with optical lens) and displayed on HDTV at the transmitted average output power of $20{\mu}W$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.533-539
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• 2015

In this paper, we designed a reconfigurable mixer for microwave broadband receiver. The proposed mixer using a anti-parallel diode is operated as a fundamental mixer or sub-harmonic mixer with respect to a control voltage. A fundamental mixer with a control voltage show a conversion loss of -10 dB, 1 dB compression point of 2.0 dBm at X-band/ Ku-band. On the other hand, it is performed as a sub-harmonic mixer with a conversion loss of -17 dB, 1 dB compression point of 2.0 dBm at Ka-band.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.7-15
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• 1989

A technique is suggested which enables the large signal current and voltage waveforms to be determined for a GaAs Schottky-Barrier diode mixer by extracting the algorithm for the nonlinear circuit analysis from the Gauss-Jacobi relaxation and the application of the Harmonic Balance Technique. Both the nonlinear and linear steps of the analysis are included. This analysis permitts accurate determination of the conversion loss for microwave mixer and the computer simulation provides an method applicable to MMIC design. The validity of the nonlinear and linear analysis is confirmed by comparing the simulation results with experimental data of the conversion loss.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.79-82
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• 2017

In this paper, we proposed the wireless communication system using millimeter-wave envelope detector. The sub-harmonic mixer based on schottky barrier diode was used in the transmitter. The receiver was used millimeter-wave envelope detector. The transmitter was composed of schottky diode sub-harmonic mixer, frequency tripler, and horn antenna. The receiver was composed of horn antenna, millimeter-wave envelope detector, low pass filter, base band amplifier, and limiting amplifier. At 1.485 Gbps and 300 GHz, the eye-diagram showed a very good performance as measured by the error free. Communication distance is reduced compared to the heterodyne receiver, but compact and lightweight is possible.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1392-1398
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• 2000

In this paper, Sub Harmonic Ring Mixer using Anti-Parallel Diode Pair is studied. Conventional mixers mix LO signal with RF signal and, obtain IF signal from the difference between LO and RF. Sub harmonic ring mixers using APDP mix RF signal with the second harmonic of LO signal, LO frequency needed for conventional receiver is reduced by 1/2.The produced mixer showed 12 dB conversion loss, and 1 dB compression point of IF signal, in respect to RF signal, was found at the 0 dBm RF signal. Isolation LO/IF and LO/RF is 24.6 dB and 22.5 dB respectively. Isolation RF/LO and LO/RF is 32.6 dB and 22.5 dB respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.105-113
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• 2010

In this paper, a 1.485 Gbps video signal transmission system using the carrier frequency of 240 GHz band was designed and simulated. The sub-harmonic mixer based on Schottky barrier diode was simulated in the transmitter and receiver. Both of heterodyne and direct detection receivers were simulated for each performance analysis. The ASK modulation was used in the transmitter and the envelop detection method was used in the receiver. The transmitter simulation results showed that the RF output power was -11.4 dBm($73{\mu}W$), when the IF input power was -3 dBm(0.5 mW) at the LO power of 7 dBm(5 mW) in sub-harmonic mixer, which corresponds to SSB(Single Side Band) conversion loss of 8.4 dB. This value is similar to the conversion loss of 8.0 dB(SSB) of VDI's commercial model WR3.4SHM(220~325 GHz) at 240 GHz. The combined transmitter and receiver simulation results showed that the recovered signal waveforms were in good agreement to the transmitted 1.485 Gbps NRZ signal.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.361-364
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• 2000

One of the problems using DCR(Direct Conversion Receiver) are DC offset, poor channel selectivity. APDP(Anti Parallel Diode Pair) can be good candidate for DCR frequency mixer due to its inherent End harmonic suppression. APDP shows good IP2 and DC suppression. This paper describe single APDP LO power characteristics, IP2, and receiver structure utilizing APDP frequency mixer

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.272-275
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• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.55-60
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• 2005

A V-band MIMIC quadruple subharmonic mixer is reported in this paper. The cascode harmonic generator is proposed for a high conversion gain. The proposed cascode harmonic generator is shown with a 4-th harmonic output characteristic that represents an average of 2.9 dB and a maximum of 4 dB higher than the conventional multiplier. The measured result of the subharmonic mixer has a conversion gain of 3_4 dB which a good conversion gain at a LO power of 13 dBm. Isolations of LO-to-IF and LO-to-RF were obtained -53.6 dB and -46.2 dB, respectively. The conversion gain of the subharmonic mixer in this study has a higher conversion gain compared with some other reports in millimeter-wave range.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.