• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.305-308
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• 2002

This paper proposes a control board that includes PNP function with extensibility and effective allocation of allocation. The object of study is to overcome limited extensity of old systems and it is to reuse the system. The system recognizes automatic subsystem from application of main system with board level that is using hardware and software co-design method. The system has both function of main-board and sub-board. So one system can operate simultaneously such as module of alien system. This system has advantages that are fast execution, according as process functional partition to hardware/ software co-design and board size is reduced as well as offer extensity of development system. We obtained good result with control board for existent Z-80 training kit.

• Speech Sciences
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• v.11 no.3
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• pp.143-156
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• 2004

In this paper, we implemented a vocabulary-independent speech recognizer using the TMS320VC33 DSP. For this implementation, we had developed very small-sized recognition engine based on diphone sub-word unit, which is especially suited for embedded applications where the system resources are severely limited. The recognition accuracy of the developed recognizer with 1 mixture per state and 4 states per diphone is 94.5% when tested on frequently-used 2000 words set. The design of the hardware was focused on minimal use of parts, which results in reduced material cost. The finally developed hardware only includes a DSP, 512 Kword flash ROM and a voice codec. In porting the recognition engine to the DSP, we introduced several methods of using data and program memory efficiently and developed the versatile software protocol for host interface. Finally, we also made an evaluation board for testing the developed hardware recognition module.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.80-83
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• 2004

Previously, in order to send information from the local controller to the display board, the hardware or software had to be handled and run through 3-phases, which include the PC-card or PC-add Board, I-F card and Sub board. This study will attempt to design a board that handles information by connecting the USB port of the PC directly to the Sub board. In addition, an MPU will be attached to the previously complex hardware circuit to design a software drive engine module, which allows for the development of new products by modifying only the software engine and not the hardware.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.1
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• pp.7-13
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• 2004

Previously, in order to send information from the local controller to the display board, the hardware or software had to be handled and run through 3-phases, which include the PC-card or PC-add Board, I/F card and Sub board. This study will attempt to design a board that handles information by connecting the USB port of the PC directly to the Sub board. In addition, an MPU will be attached to the previously complex hardware circuit to design a software drive engine module, which allows for the development of new products by modifying only the software engine and not the hardware.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.339-340
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• 2015

본 논문에서는 HVDC 제어 시스템의 기능 검증을 위해 구축한 RTDS 기반의 HILS(Hardware-In-the Loop Simulation)시스템 및 시험 결과를 소개하였다. MMC 기반 VSC HVDC는 다수의 직렬 연결된 SM(Sub-Module)을 개별 제어해야 하므로 기존의 LCC HVDC 및 2/3-Level 컨버터 기반의 VSC HVDC와 같은 설비들보다 훨씬 더 복잡한 VBE 구조를 가지고 있다. 또한 짧은 시간 내에 정밀한 제어가 가능해야 하므로 높은 제어 정밀도가 요구된다. (주)효성에서는 제어 시스템의 성능 검증을 위해 RTDS 기반의 HILS(Hardware-In-the Loop Simulation)시스템을 구축하였으며, 이를 이용하여 HVDC 제어 시스템의 성능 시험을 수행하였다. 본 논문에서는 구축된 RTDS 기반의 HILS 시스템 및 시험 결과를 소개하였다.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.2
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• pp.61-68
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• 2007

In a naval combat system, the information processing node is a key functional equipment and performs major combat management functions including control sensor and weapon systems. Therefore, a failure of one of the node causes fatal impacts on overall combat system capability. There were many methodologies to enhance system availability by reducing the impact of system failure like a fault tolerant method. This paper proposes a fault tolerant mechanism for information processing node using a replication algorithm with hardware duplication. The mechanism is designed as a generic algorithm and does not require any special hardware. Therefore all applications in combat system can use this functionality. The asynchronous characteristic of this mechanism provides the capability to adapt this algorithm to the module which has low performance hardware.

• Journal of Information Processing Systems
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• v.17 no.2
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• pp.227-241
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• 2021

Object detection techniques based on deep learning such as YOLO have high detection performance and precision in a single channel video stream. In order to expand to multiple channel object detection in real-time, however, high-performance hardware is required. In this paper, we propose a novel back-end server framework, a real-time AI vision platform (RAVIP), which can extend the object detection function from single channel to simultaneous multi-channels, which can work well even in low-end server hardware. RAVIP assembles appropriate component modules from the RODEM (real-time object detection module) Base to create per-channel instances for each channel, enabling efficient parallelization of object detection instances on limited hardware resources through continuous monitoring with respect to resource utilization. Through practical experiments, RAVIP shows that it is possible to optimize CPU, GPU, and memory utilization while performing object detection service in a multi-channel situation. In addition, it has been proven that RAVIP can provide object detection services with 25 FPS for all 16 channels at the same time.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

• Korean Journal of Geomatics
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• v.3 no.2
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• pp.99-106
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• 2004

In order to meet the users' demand, who needs faster and more accurate data in geographic information, it is necessary to obtain and process the data more effectively. Now more effective data obtainments about geographic information is possible through the development of integration technology, which is applied to the field of geographic information, as well as through the development of hardware and software engineering. With the fast and precise correction and update, the development of integrate technology can bring the reduction of the time and money. To obtain fast and precise geographic information using Aerial Photogrammetry method, it is necessary to develop Airborne GPS/INS integration system, which makes GCP to the minimum. For this reason, this study has tried to develop a system which could unite and process both GPS and INS data. For this matter, code-processing module for DGPS and OTF initializaion module, which can decide integer ambiguity even in motion, have been developed. And also, continuous kinematic carrier-processing module has been developed to calculate the location at the moment of filming. In addition, this study suggests a possibility of using a module, which can unite GPS and INS, using Kalman filtering, and also shows the INS navigation theory.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2
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• pp.30-39
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• 1995

In this paper, study on implementation of FFT analyzer applied to CAT, A/D conversion module, DSP module and VXIbus interface module are implemented in hardware and calculation program and control software are implemented in DSP module and VXIbus interface module, respectively. The control of the modules using PC is realized in software. The real time bandwidth of the FFT analyzing device is 100KHz. At sampling rate of 200KHz and with 2048 point FFT, the result of applying sine, triangular and rectangular wave of 20KHz to FFT analyzing device is compared with the FFT analyzed results of Hewlett-Packard 3562A dynamic output range of -40dBV- +30dBV, correct results are obtained and results of applying 10KHz, 20KHz and 50KHz input are compared and the correct values are obtained.