• Journal of Internet Computing and Services
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• v.14 no.1
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• pp.15-22
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• 2013

WAVE(Wireless Access for Vehicular Environment) is new concepts and Vehicles communications technology using for ITS(Intelligent Transportation Systems) service by IEEE standard 802.11p. Also it increases the efficiency and safety of the traffic on the road. However, the efficiency of Scrambler bit computational algorithms of OFDM modulation in WAVE systems will fall as it is not able to process in parallel in terms of hardware and software. This paper proposes an algorithm to configure 64-bits matrix table in scambler bit computation as well as an algorithm to compute 64-bits matrix table and input data in parallel. The proposed algorithm on this thesis is executed using 64-bits matrix table. In the result, the processing speed for 1 and 1000 times is improved about 40.08% ~ 40.27% and processing rate per sec is performed more than 468.35 compared to bit operation scramble. And processing speed for 1 and 1000 times is improved about 7.53% ~ 7.84% and processing rate per sec is performed more than 91.44 compared to 32-bits operation scramble. Therefore, if the 64 bit-CPU is used for 64-bits executable scramble algorithm, it is improved more than 40% compare to 32-bits scrambler.

• Journal of Practical Engineering Education
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• v.5 no.2
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• pp.101-107
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• 2013

Clickers that are personal response systems are a technology used to promote active learning and most research on the benefits of using clickers has shown that students become engaged and enjoy using them. But, existing clickers consisting of hardware devices and aggregation software provide simple response and aggregation function and it costs a lot. In this paper, in order to resolve the limitation of the existing clickers, we've designed and implemented the Smart Clicker consisting of a smartphone application for students and a web application & a MFC program for professors. Students can answer professor's questions with O/X or numbers or text and even ask questions with text messaging by using Smart Clicker in the classroom. Professors can see students' answers or questions immediately and check up students' response participation rate on the web page. Besides, the Smart Clicker will help professors actively engage students during the entire class period and gauge their level of understanding of the material being presented, and provide prompt feedback to student questions. As a result, we expect that quality of education will be increased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.3
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• pp.411-418
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• 2017

In the domestic case, although technological capabilities are recognized globally in the IT field, it is actually that the technical capabilities of the domestic leisure ship market which is formed mainly by fishing vessels are not beyond their technical capabilities At the point where the GNP of our country already goes over 22,000 dollars, the demand for the products related to the middle and small leisure boats is gradually increasing, but most of the high added value products depend on the imports from U.S.A. and Europe. And in case of the cars, with the Car Navigation as the start, products which satisfies various demands of the users are coming out in large quantity and now the IT technology is the necessity which can not be lived without in the car industry. Thus, if the digital ship navigator which jointed the recent ICT technology which was applied to the land for the domestic middle and small leisure ships by utilizing the embedded hardware technology and mapping technology which are credible is developed and distributed, it will become not only the opportunity to improve the industry related to middle and small ship IT, but also, the export about overseas market can be expected.

• Journal of The Korean Association of Information Education
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• v.21 no.1
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• pp.41-55
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• 2017

The physical computing education, as the emerging field, is a form of education that helps learners to develop the attitude of scientific inquiry by developing meaningful and creative output through the integration of hardware and software elements. Based on the literature, the authors of the study used science experience, school support and learning flow as the variables that predict the outcome variable which is the attitude of scientific inquiry. The authors collected data from 64 fourth and sixth graders who studied physical computing at an institution for the gifted and talented in Korea and then analyzed them using descriptive statistics, correlation, multiple regression and simple mediation analysis methods. As a result, science experience and learning flow significantly predicted the attitude of scientific inquiry. In addition, learning flow mediated the relationship between science experience and the attitude of scientific inquiry, and the relationship between school support and the attitude of scientific inquiry. Based on these results, the authors propose that to promote the attitude of scientific inquiry in physical computing education, strategies must be implemented for improving science experience, school support and learning flow in instructional design.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.269-272
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• 2006

Game industry is one of the most popular sector in the world cultural industries in the digital era. 2D and 3D Animation with development of computer technology it. Because Animation needs to show real motion image. The computer hardware and software technique quick change it leads and 2D and 3D the animation is the tendency which provides the growth which is infinite. But recently Game graphic design have a trend 3D Game that is absorbed and easy handling. 2D Game Character is changing to 3D Game Character more and more. This thesis have significant the real motion capture of 3D Game Character and the types, the shapes of 3D Game Character animation. First of all this thesis will define about 3D Game Character as well it will be show examples of real motion capture also it will proposal data of real motion capture. Therefore it will be bring the high technology Animation industry with Digital Contents industry. also hope for the growth of Game Character Animation process and 3D Game Character Animation in Game industry as well contents industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Journal of Korea Multimedia Society
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• v.2 no.3
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• pp.277-288
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• 1999

A distributed multimedia school system is developed for the multimedia classroom at high school and university. The system is designed and implemented for students to improve the learning efficiency through the personalized multimedia contents and pace of learning. The previously developed multimedia information retrieval systems have some limitations on being applied to the multimedia classroom: expensive cost per stream or poor retrieval quality inappropriate for education, unscalability of system and service, unfamiliar proprietary client environment, and difficulty for teachers to use the authoring tools and manage the authored teaching materials. The system we developed overcomes the above problems. It is so scalable as to be applicable not only to a segmented classroom but also to the world wide Internet. The stream server is one of the components of the system: stream servers clients, a service gateway system, and a authoring management system. This paper describes the design and implementation of the stream server. A single stream server can simultaneously playback the multimedia streams as many as clients at one classroom. This is achieved only by the software engine without any changes of the hardware architecture. The systematic coupling with other components gives the scalability of the system and the flexibility of services.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.726-734
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• 2015

Relational databases used by structuralizing data are the most widely used in data management at present. However, in relational databases, service becomes slower as the amount of data increases because of constraints in the reading and writing operations to save or query data. Furthermore, when a new task is added, the database grows and, consequently, requires additional infrastructure, such as parallel configuration of hardware, CPU, memory, and network, to support smooth operation. In this paper, in order to improve the web information services that are slowing down due to increase of data in the relational databases, we implemented a model to extract a large amount of data quickly and safely for users by processing Hadoop Distributed File System (HDFS) files after sending data to HDFSs and unifying and reconstructing the data. We implemented our model in a Web-based civil affairs system that stores image files, which is irregular data processing. Our proposed system's data processing was found to be 0.4 sec faster than that of a relational database system. Thus, we found that it is possible to support Web information services with a Hadoop-based big data processing technique in order to process a large amount of data, as in conventional relational databases. Furthermore, since Hadoop is open source, our model has the advantage of reducing software costs. The proposed system is expected to be used as a model for Web services that provide fast information processing for organizations that require efficient processing of big data because of the increase in the size of conventional relational databases.