• International Journal of Fluid Machinery and Systems
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• v.5 no.3
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• pp.134-142
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• 2012

The competition to deliver ultra-low emitting vehicles at a reasonable cost is driving the automotive industry to invest significant manpower and test laboratory resources in the design optimization of increasingly complex exhaust after-treatment systems. Optimization can no longer be based on traditional approaches, which are intensive in hardware use and laboratory testing. The CFD is in high demand for the analysis and design in order to reduce developing cost and time consuming in experiments. This paper describes the development of a comprehensive practical model based on experiments for simulating the performance of automotive three-way catalytic converters, which are employed to reduce engine exhaust emissions. An experiment is conducted to measure species concentrations before and after catalytic converter for different loads on engine. The model simulates the emission system behavior by using an exhaust system heat conservation and catalyst chemical kinetic sub-model. CFD simulation is used to study the performance of automotive catalytic converter. The substrate is modeled as a porous media in FLUENT and the standard k-e model is used for turbulence. The flow pattern is changed from axial to radial by changing the substrate model inside the catalytic converter and the flow distribution and the conversion efficiency of CO, HC and NOx are achieved first, and the predictions are in good agreement with the experimental measurements. It is found that the conversion from axial to radial flow makes the catalytic converter more efficient. These studies help to understand better the performance of the catalytic converter in order to optimize the converter design.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.88-95
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• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.188-194
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• 2007

In order to become ubiquitous world, the compatibility of wireless machines has become the significant characteristic of a communication terminal. Thus, SDR is the most necessary technology and standard. However, among the environment which has different communication protocol, it's difficult to make a terminal with only hardware using ASIC or SoC. This paper suggests the processor that can accelerate several communication protocol. It can be connected with main-processor, and it is specialized PHY layer of network The C-program that is modeled with the wireless protocol IEEE802.11a and IEEE802.11b which are based on widely used modulation way; OFDM and CDM is compiled with ARM cross compiler and done simulation and profiling with Simplescalar-Arm version. The result of profiling, most operations were Viterbi operations and complex floating point operations. According to this result we suggested a co-processor which can accelerate Viterbi operations and complex floating point operations and added instructions. These instructions are simulated with Simplescalar-Arm version. The result of this simulation, comparing with computing only one ARM core, the operations of Viterbi improved as fast as 4.5 times. And the operations of complex floating point improved as fast as twice. The operations of IEEE802.11a are 3 times faster, and the operations of IEEE802.11b are 1.5 times faster.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.160-160
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• 2017

자동화 기술을 통한 한국형 스마트팜의 발전이 비약적으로 이루어지고 있는 가운데 무인화를 위한 지능적인 스마트 시설환경 관찰 및 분석에 대한 요구가 점점 증가 하고 있다. 스마트 시설환경에서 취득 가능한 시계열 데이터는 온도, 습도, 조도, CO2, 토양 수분, 환기량 등 다양하다. 시스템의 경계가 명확함에도 해당 속성의 특성상 타임도메인과 공간도메인 상에서 정확한 추정 또는 예측이 난해하다. 시설 환경에 접목이 증가하고 있는 지능형 관리 기술 구현을 위해선 시계열 공간 데이터에 대한 신속하고 정확한 정량화 기술이 필수적이라 할 수 있다. 이러한 기술적인 요구사항을 해결하고자 시도되는 다양한 방법 중에서 공간 분해능 향상을 위한 다지점 계측 메트릭스를 실험적으로 구성하였다. $50m{\times}100m$의 단면적인 연동 딸기 온실을 대상으로 $3{\times}3{\times}3$의 3차원 환경 인자 계측 매트릭스를 설치하였다. 1 Hz의 주기로 4가지 환경인자(온도, 습도, 조도, CO2)를 계측하였으며, 계측 하는 시점과 동시에 병렬적으로 공간통계법을 이용하여 미지의 지점에 대한 환경 인자들을 실시간으로 추정하였다. 선행적으로 50 cm 공간 분해능에 대응하기 위하여 Kriging interpolation법을 횡단면에 대하여 분석한 후 다시 종단면에 대하여 분석하였다. 3 Ghz에 해당하는 연산 능력을 보유한 컴퓨터에서 1초 동안 획득한 데이터에 대한 분석을 마치는데 소요되는 시간이 15초 내외로 나타났다. 이는 해당 알고리즘의 매우 높은 시간 복잡도(Order of $O=O^3$)에 기인하는 것으로 다양한 시설 환경의 관리 방법론에 적절히 대응하기에 한계가 있다 할 수 있다. 실시간으로 시간 복잡도가 높은 연산을 수행하기 위한 기술적인 과제를 해결하고자, 근래에 관심이 증가하고 있는 NVIDIA 사에서 제공하는 CUDA 엔진과 Apple사의 제안을 시작으로 하여 공개 소프트웨어 개발 컨소시엄인 크로노스 그룹에서 제공하는 OpenCL 엔진을 비교 분석하였다. CUDA 엔진은 GPU(Graphics Processing Unit)에서 정보 분석 프로그램의 연산 집약적인 부분만을 담당하여 신속한 결과를 산출할 수 있는 라이브러리이며 해당 하드웨어를 구비하였을 때 사용이 가능하다. 반면, OpenCL은 CUDA 엔진이 특정 하드웨어에서 구동이 되는 한계를 극복하고자 하드웨어에 비의존적인 라이브러리를 제공하는 것이 다르며 클러스터링 기술과 연계를 통해 낮은 하드웨어 성능으로 인한 단점을 극복하고자 하였다. 본 연구에서는 CUDA 8.0(https://developer.nvidia.com/cuda-downloads)버전과 Pascal Titan X(NVIDIA, CA, USA)를 사용한 방법과 OpenCL 1.2(https://www.khronos.org/opencl/)버전과 Samsung Exynos5422 칩을 장착한 ODROID-XU4(Hardkernel, AnYang, Korea)를 사용한 방법을 비교 분석하였다. 50 cm의 공간 분해능에 대응하기 위한 4차원 행렬($100{\times}200{\times}5{\times}4$)에 대하여 정수 지수화를 위한 Quantization을 거쳐 CUDA 엔진과 OpenCL 엔진을 적용한 비교한 결과, CUDA 엔진은 1초 내외, OpenCL 엔진의 경우 5초 내외의 연산 속도를 보였다. CUDA 엔진의 경우 비용측면에서 약 10배, 전력 소모 측면에서 20배 이상 소요되었다. 따라서 우선적으로 OpenCL 엔진 기반 하드웨어 가속 기술 최적화 연구를 통해 스마트 시설환경 실시간 시뮬레이션 기술 도입을 위한 기술적 과제를 풀어갈 것이다.

• Journal of the Korean Association of Geographic Information Studies
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• v.19 no.1
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• pp.180-196
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• 2016

To minimize the damage from disasters, various aspects of prevention, preparation, and response, etc. are being managed. Even though prevention and preparation are well conducted, irresistible calamities such as natural disasters may cause unexpected damage. Therefore, a system that can share the identical disaster information based on prompt disaster management and prediction must be developed and constructed for integrated disaster management. Especially, for a prompt disaster response, the same information needs to be shared between the related organization and the disaster prevention personnel such as on-site officials. Recent disaster management systems use high-capacity geographic information or other various factors for accurate disaster predictions. In case of using a recently constructed or researched 3D GIS, the system may not be used in some cases due to conflicts with hardware, etc. Thus, even though response information is secured using prediction simulation in advance, it is essentially difficult in some cases to share the common information when the system cannot be utilized or the extension of the corresponding data cannot be read. Therefore, this study aims to construct a system for dealing with disasters that shares the same prompt and accurate information in compliance with common data formats. The system is expected to reduce the existing disaster response time and minimize human and physical damage by assisting decision making through prompt responses.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.9
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• pp.935-939
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• 2015

This paper describes sensorless speed control of brushless DC motors by using direct torque control. Direct torque control offers fast torque response, robust specification of parameter changes, and lower hardware and processing costs compared to vector-controlled drives. In this paper, the current error compensation method is applied to the sensorless speed control of a brushless DC motor. Through this control technique, the controlled stator voltage is applied to the brushless DC motor such that the error between the stator currents in the mathematical model and the actual motor can be forced to decay to zero as time proceeds, and therefore, the motor speed approaches the setting value. This paper discusses the composition of the controller, which can carry out robust speed control without any proportional-integral (PI) controllers. The simulation results show that the control system has good dynamic speed and load responses at wide ranges of speed.

• Science of Emotion and Sensibility
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• v.4 no.2
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• pp.57-62
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• 2001

In the car design process, Interior color scheme is one of the important factors that determined consumer's emotional evaluation with a car styling. The systematic research on the car interior color planning may be not achieved in spite of its importance because it is difficult to simulate color scheme before deciding final prototype. The various alternative of color scheme can be simulated and evaluated in early stage of car design process based on upgraded performance of computer hardware and advance41 co-work system. This study proposed a color coordinate support system for car interior color design to support designer based on emotional scale of color image. Color coordinate support system have four kinds of module, that is, the information acquisition module for gathering user's emotional data, the evaluation module for analyzing relation of color impressions and color attributes, the simulation module for supporting color coordinate design, and the evaluation support module for testing final color alternatives.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.