• Asia-Pacific Journal of Business Venturing and Entrepreneurship
• /
• v.7 no.4
• /
• pp.131-141
• /
• 2012

The miracle of Korean economic development is the benchmarking for the developing countries. Among them, the STP of Science and technology area is very important case they tring to learn from Deadeok, Korea. Ecuador and Kazakhstan have the huge natural resources and they have interested in the model of Daedeok STP. This paper study about their needs and Daedeok's capability, and effective implementing factors. This paper suggest a six one based on the Daedeok Innopolis experiences for the successful local STP. First, most important thing is human resource development strategy for the knowledge and technology transfer. Second, the construction of Engineering Center for the collaboration of industry and academy is needed. This is important to have a bargaining power to the appropriate technology transfer. Third, they need a hardware and software infrastructure to the technology commercialization. It include a incubator, manager, and complimentary asset. Fourth, they have to connect with market closely for the venture creation and growth. Fifth, the clustering is realized by the STP construction. Lastly, leadership is critical factor to the absorptive capacity.

• Nuclear Medicine and Molecular Imaging
• /
• v.42 no.2
• /
• pp.153-163
• /
• 2008

Medical imaging modalities to image either anatomical structure or functional processes have developed along somewhat independent paths. Functional images with single photon emission computed tomography (SPECT) and positron emission tomography (PET) are playing an increasingly important role in the diagnosis and staging of malignant disease, image-guided therapy planning, and treatment monitoring. SPECT and PET complement the more conventional anatomic imaging modalities of computed tomography (CT) and magnetic resonance (MR) imaging. When the functional imaging modality was combined with the anatomic imaging modality, the multimodality can help both identify and localize functional abnormalities. Combining PET with a high-resolution anatomical imaging modality such as CT can resolve the localization issue as long as the images from the two modalities are accurately coregistered. Software-based registration techniques have difficulty accounting for differences in patient positioning and involuntary movement of internal organs, often necessitating labor-intensive nonlinear mapping that may not converge to a satisfactory result. These challenges have recently been addressed by the introduction of the combined PET/CT scanner and SPECT/CT scanner, a hardware-oriented approach to image fusion. Combined PET/CT and SPECT/CT devices are playing an increasingly important role in the diagnosis and staging of human disease. The paper will review the development of multi modality instrumentations for clinical use from conception to present-day technology and the application software.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.168-175
• /
• 2013

Color consistency in stereoscopic contents is important for 3D display systems. Even with a stereo camera of the same model and with the same hardware settings, complex color discrepancies occur when acquiring high quality stereo images. In this paper, we propose an integrated color matching method that use cumulative histogram in global matching and estimated 3D-distance for the stage of local matching. The distance between the current pixel and the target local region is computed using depth information and the spatial distance in the 2D image plane. The 3D-distance is then used to determine the similarity between the current pixel and the target local region. The overall algorithm is described as follow; First, the cumulative histogram matching is introduced for reducing global color discrepancies. Then, the proposed local color matching is established for reducing local discrepancies. Finally, a weight-based combination of global and local matching is computed. Experimental results show the proposed algorithm has improved global and local error correction performance for stereoscopic contents with respect to other approaches.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.43 no.1 s.307
• /
• pp.45-52
• /
• 2006

In this paper, a real-time stereoscopic image conversion method using a single frame from a 2-D image is proposed. The Stereoscopic image is generated by creating depth map using vortical position information and parallax processing. For a real-time processing of stereoscopic conversion and reduction of hardware complexity, it uses image sampling, object segmentation by standardizing luminance and depth map generation by boundary scan. The proposed method offers realistic 3-D effect regardless of the direction, velocity and scene conversion of the 2-D image. It offers effective stereoscopic conversion using images suitable conditions assumed in this paper such as recorded image at long distance, landscape and panorama photo because it creates different depth sense using vertical position information from a single frame. The proposed method can be applied to still image because it uses a single frame from a 2-D image. The proposed method has been evaluated using visual test and APD for comparing the stereoscopic image of the proposed method with that of MTD. It is confirmed that stereoscopic images conversed by the proposed method offers 3-D effect regardless of the direction and velocity of the 2-D image.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.6
• /
• pp.25-35
• /
• 1998

The control system architecture in switching systems have undergone numerous changes to provide various call processing capability needed in telecommunication services. During call processing in a distributed switching control environment, the delay effect due to communication among main processors or peripheral controllers is one of the limiting factors which affect the system performance. In this paper, we propose a performance model for an IPC(Inter Processor Communication) interface hardware block which is required on the ATM cell-based message processing in a distributed ATM exchange system, and analyze the primary causes which affect the processor performance through the simulation. Consequently, It can be shown that the local CPU of the several components(resources) related to the IPC scheme is a bottleneck factor in achieving the maximum system performance from the simulation results, such as the utilization of each processing component according to the change of the input message rate, and the queue length and processing delay according to input message rate. And we also give some useful results such as the maximum message processing capacity according to the change of the performance of local CPU, and the local CPU maximum throughput according to the change of average message length, which is applicable as a reference data for the improvement or expansion of the ATM control system.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.4
• /
• pp.37-47
• /
• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.48-56
• /
• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.37-47
• /
• 2011

Real picture like high quality computer graphic is widely used in various fields and shader processor, a key part of a graphic processor, has been advanced to programmable unified shader. However, The existing graphic processors have been optimized to commercial algorithms, so development of an algorithm which is not based on it requires an independent shader processor. In this paper, we have designed and implemented a control unit to support high quality 3 dimensional computer graphic image on programmable integrated shader processor. We have done evaluation through functional level simulation of designed control unit. Hardware resource usage rate are measured by implementing directly on FPGA Virtex-4 and execution speed are verified by applying ASIC library. the result of an evaluation shows that the control unit has the commands more about 1.5 times compared to the other shader processors that is a behavior similar to the control unit and with a number of processing units used in a shader processor, compared with the other processors, overall performance of the control unit is improved about 3.1 GFLOPS.

• Journal of Korean Society of Transportation
• /
• v.33 no.1
• /
• pp.70-80
• /
• 2015

In recent years, tram has been the focus of a new mode of public transportation that can solve traffic jams and decrease public transit usage and environmental problem. This research is in the works to develop a tram signal controller and signal control strategies, and aim to resolve the problem of what could happen if a tram system was installed in general road. We developed the hierarchical signal control strategies to obtain a minimum tram bandwidth and to minimize vehicle delay, in order to perform a priority control to include passive and active signal priority control strategies. The strategies was produced for S/W and H/W, it is based in standard traffic signal controller. We conducted a micro simulation test to evaluate the hierarchical signal control strategies, which showed that the developed optimization model is effective to prevent a tram's stop in intersection, to reduce a tram's travel time and vehicle's delay.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.4
• /
• pp.78-86
• /
• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.