• 전기전자학회논문지
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• 제22권1호
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• pp.197-200
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• 2018

본 논문에서는 하드웨어레벨로 구현이 어렵고 속도가 느린 sigmoid 함수를 PLAN을 이용하여 근사치로 출력하였다. 이를 MLP 구조의 활성화 함수로 사용하여 자원소모를 줄이고 속도를 개선하고자 하였다. 본 논문에서 제안하는 방법은 $5{\times}5$크기의 숫자 인식에 약 95%의 정확도를 유지하면서 GPGPU보다 약 1.83배의 빠른 속도를 보였다. 또한 MLPA가속기와 비슷한 자원을 사용함에도 더 많은 뉴런을 사용하여 높은 정확도에 빠른 속도로 수렴하는 것을 확인하였다.

• International Journal of Automotive Technology
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• 제3권4호
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• pp.129-135
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• 2002

Durability estimation of a prototype vehicle has traditionally relied heavily on accelerated durability tests using predefined proving grounds or rig tests using a road simulator. By use of those tests, it is very difficult to predict durability failures in actual service environments. This motivated the development of an integrated CAE (Computer Aided Engineering) methodology for the durability estimation of a prototype vehicle in actual service environments. Since expensive computational costs such as computation time and hardware resources are required for a full vehicle simulation in those environments with a very long span of event time, the conventional CAE methodologies have little feasibility. An efficient computational methodology for durability estimations is applied with theoretical developments. The effectiveness of the proposed methodology is shown by the comparison of results of the typical actual service environment such as the city mode with those of the typical accelerated durability test over the Belgian road.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.60-67
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• 2015

This paper proposes an image-dependent color image enhancement method that uses adaptive luminance enhancement and color emphasis. It effectively enhances details of low-light regions while maintaining well-balanced luminance and color information. To compare the structure similarity and naturalness, we used the tone mapped image quality index (TMQI). The proposed method maintained better structure similarity in the enhanced image than did the space-variant luminance map (SVLM) method or the adaptive and integrated neighborhood dependent approach for nonlinear enhancement (AINDANE). The proposed method required the smallest computation time among the three algorithms. The proposed method can be easily implemented using the field-programmable gate array (FPGA), with low hardware resources and with better performance in terms of similarity.

• 한국위성정보통신학회논문지
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• 제10권2호
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• pp.115-120
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• 2015

지금까지 저궤도 위성의 자세제어 SW는 자세제어 연산을 위해서 CPU Resource로 있는 FPU를 사용하였으며, 이 결과 SW Throughput의 상당 부분이 행렬 곱셈 연산에 사용 되었다. 향후 위성에서 제어 주기가 더 짧아지고, 연산 량이 증가하면, 심각한 영향을 받을 수 있기 때문에 곱셈 전용 HW구현이 필요하게 되었다. 본 논문에서는 부동소수점 행렬 곱셈을 전용으로 수행하는 HW를 구현 및 성능 측정을 수행한 결과를 제시하며 추가적인 성능 향상을 위한 방법들과 향후 과제를 언급한다.

• 조명전기설비학회논문지
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• 제22권7호
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• pp.1-6
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• 2008

In industrial fields, human works are being replaced by robots. However, as the use of robots is limited in the process industry where they are operated fixedly, humanoid robots with wide applications need to be developed. Currently a great deal of research is being conducted on humanoid robots with the object of replacing humans in the workplace. However, because of the lack of relevant hardware and difficulty in mechanical parts, only very simple and limited progress is being made. In an effort to overcome these limitations, the purpose of the present study is to develop a kinematical mechanism and a controller. To this end, master arms with 3 degrees-of-freedom for the shoulders and the arms were composed which were able to reproduce human-like motions by simulating the characteristics of joint variables and the trajectory of the end-effector.

• 한국멀티미디어학회논문지
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• 제17권3호
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• pp.353-363
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• 2014

Cloud computing is an internet-based technology, providing services to the virtualized IT environment, and allowing users to add or remove resources of hardware or software at their discretion. Since Cloud computing can construct virtually integrated environments out of multiple local computing environments, various information services can be provided by it. In addition, state organizations also strive to build the cloud computing environments due to the benefits of reduced costs to introduce the system and of reduced time to build and provide the IT services. This study suggests a web-based cloud computing system for the computing environments, to be applied for the Korean National Health and Nutrition Examination Survey (KNHANES) by the Ministry of Health and Welfare, Republic of Korea.

• Journal of Communications and Networks
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• 제1권2호
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• pp.134-142
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• 1999

We have developed fully functional Video Server and Client applications which can transmit, receive, decompress and display compressed video over various networks. Our video trans-port allows dynamic rate control feedback, loss detection, and repair requests from Clients to the Server. Our experiments show how feedvack-before-degradation scheme for rate adaptation maintains good display frame-rate for video playback. We show how the playback degradation(reduction in display frame-rate) oc-curs and what happens if corrective measures are not taken to im-prove the situation. The degradation is attributed to the increased internal kernel buffering which consumes scarce CPU resources. We demontrate with our experimental results that ServerNet, with improved hardware delivery guarantees, can significantly reduce host CPU resource consumption while serving video streams. We present the maximum number of streams which can be served for each of ATM and ServerNet interconnects. The appropriate user-level packet size for the video server are also determined for each case.

• 한국통신학회논문지
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• 제21권11호
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• pp.2966-2977
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• 1996

As design of very large circuits is made possible by rapid development of VLSI technologies, efficient fault simulation is needed. Ingeneral, fault simulation requires many computer resources. As general-purpose multiprocessors become more common and affordable, these seem to be an attractive and effective alternative for fault simulation. Efficient fault simulation of synchronous sequential circuits has been reported to be attainably by using a linear iterative array model for such a circuit, and combining parallel fault simulation with russogate fault simulation. Such fault simulation algorithm is parallelized on a general-purpose multiprocessor with shard memory for acceleration of fault simulation. Through the experimenal study, the effect of the number of processors on speed-up of simulation, processor utilization, and the effect of multiprocessor hardware on simulation performance are studied. Some results for experiments with benchmark circuits are shown.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.761-762
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• 2008

This paper presents a hardware accelerator for accelerating vector graphics applications based on the OpenVG standard. Since our design mainly targets embedded applications, we focus on efficient uses of limited resources, especially the memory bandwidth. The designed accelerator can process the images of $640{\times}240$ pixels with moderate complexity at the rate of 30 frames per second.

• 전자공학회논문지A
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• 제33A권5호
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• pp.188-202
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• 1996

In this paper, we propose a symmetrical pseudo faulty processing elements genration technique to improve the overall reliability of arrays with fixed hardware resources on the fault tolerant VLSI arrays based on single-track switches. We have analyzed the reliability of fault tolerant VLSI arrays and designed control logic for real-tiem reconfiguration. Applying this technique to reconfiguration of VLSI 2-D arrays, we have found that the proposed scheme achieves a higher reliability than the previus methods of similar condition. And we have found that the results of reliability analyzed by mathematic computation are very close to simulated ones. Furthermore, the time overhead for reconfiguration is independent of the array size because the control for reconfiguration is distributively executed by each processing elements. And the proposed scheme has an advantage which maintained properties of VLSI arrays by keeping the locality of interconnections as high as possible even after the reconfiguration.