• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.307-311
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• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.

• Journal of IKEEE
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• v.22 no.1
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• pp.197-200
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• 2018

In this paper, sigmoid function, which is difficult to implement at hardware level and has a slow speed, is approximated by using PLAN. We use this as an activation function of MLP structure to reduce resource consumption and speed up. In this paper, we show that the proposed method maintains 95% accuracy in $5{\times}5$ size recognition and 1.83 times faster than GPGPU. We have found that even with similar resources as MLPA accelerators, we use more neurons and converge at higher accuracy and higher speed.

• International Journal of Automotive Technology
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• v.3 no.4
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• pp.129-135
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• 2002

Durability estimation of a prototype vehicle has traditionally relied heavily on accelerated durability tests using predefined proving grounds or rig tests using a road simulator. By use of those tests, it is very difficult to predict durability failures in actual service environments. This motivated the development of an integrated CAE (Computer Aided Engineering) methodology for the durability estimation of a prototype vehicle in actual service environments. Since expensive computational costs such as computation time and hardware resources are required for a full vehicle simulation in those environments with a very long span of event time, the conventional CAE methodologies have little feasibility. An efficient computational methodology for durability estimations is applied with theoretical developments. The effectiveness of the proposed methodology is shown by the comparison of results of the typical actual service environment such as the city mode with those of the typical accelerated durability test over the Belgian road.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.60-67
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• 2015

This paper proposes an image-dependent color image enhancement method that uses adaptive luminance enhancement and color emphasis. It effectively enhances details of low-light regions while maintaining well-balanced luminance and color information. To compare the structure similarity and naturalness, we used the tone mapped image quality index (TMQI). The proposed method maintained better structure similarity in the enhanced image than did the space-variant luminance map (SVLM) method or the adaptive and integrated neighborhood dependent approach for nonlinear enhancement (AINDANE). The proposed method required the smallest computation time among the three algorithms. The proposed method can be easily implemented using the field-programmable gate array (FPGA), with low hardware resources and with better performance in terms of similarity.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.115-120
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• 2015

Until now, AOCS SW has used FPU which is one of CPU resources for satellite attitude control. And most of the SW Throughput was consumed to calculate Matrix Multiply. As SW throughput margin is decreasing seriously with shorter control period and more computational burden at next satellite programs, a dedicated HW matrix multiplier is absolutely required. This paper represents results of HW implementation & performance measurement and mentions several techniques for performance improvement, further works.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.7
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• pp.1-6
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• 2008

In industrial fields, human works are being replaced by robots. However, as the use of robots is limited in the process industry where they are operated fixedly, humanoid robots with wide applications need to be developed. Currently a great deal of research is being conducted on humanoid robots with the object of replacing humans in the workplace. However, because of the lack of relevant hardware and difficulty in mechanical parts, only very simple and limited progress is being made. In an effort to overcome these limitations, the purpose of the present study is to develop a kinematical mechanism and a controller. To this end, master arms with 3 degrees-of-freedom for the shoulders and the arms were composed which were able to reproduce human-like motions by simulating the characteristics of joint variables and the trajectory of the end-effector.

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.353-363
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• 2014

Cloud computing is an internet-based technology, providing services to the virtualized IT environment, and allowing users to add or remove resources of hardware or software at their discretion. Since Cloud computing can construct virtually integrated environments out of multiple local computing environments, various information services can be provided by it. In addition, state organizations also strive to build the cloud computing environments due to the benefits of reduced costs to introduce the system and of reduced time to build and provide the IT services. This study suggests a web-based cloud computing system for the computing environments, to be applied for the Korean National Health and Nutrition Examination Survey (KNHANES) by the Ministry of Health and Welfare, Republic of Korea.

• Journal of Communications and Networks
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• v.1 no.2
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• pp.134-142
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• 1999

We have developed fully functional Video Server and Client applications which can transmit, receive, decompress and display compressed video over various networks. Our video trans-port allows dynamic rate control feedback, loss detection, and repair requests from Clients to the Server. Our experiments show how feedvack-before-degradation scheme for rate adaptation maintains good display frame-rate for video playback. We show how the playback degradation(reduction in display frame-rate) oc-curs and what happens if corrective measures are not taken to im-prove the situation. The degradation is attributed to the increased internal kernel buffering which consumes scarce CPU resources. We demontrate with our experimental results that ServerNet, with improved hardware delivery guarantees, can significantly reduce host CPU resource consumption while serving video streams. We present the maximum number of streams which can be served for each of ATM and ServerNet interconnects. The appropriate user-level packet size for the video server are also determined for each case.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2966-2977
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• 1996

As design of very large circuits is made possible by rapid development of VLSI technologies, efficient fault simulation is needed. Ingeneral, fault simulation requires many computer resources. As general-purpose multiprocessors become more common and affordable, these seem to be an attractive and effective alternative for fault simulation. Efficient fault simulation of synchronous sequential circuits has been reported to be attainably by using a linear iterative array model for such a circuit, and combining parallel fault simulation with russogate fault simulation. Such fault simulation algorithm is parallelized on a general-purpose multiprocessor with shard memory for acceleration of fault simulation. Through the experimenal study, the effect of the number of processors on speed-up of simulation, processor utilization, and the effect of multiprocessor hardware on simulation performance are studied. Some results for experiments with benchmark circuits are shown.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.761-762
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• 2008

This paper presents a hardware accelerator for accelerating vector graphics applications based on the OpenVG standard. Since our design mainly targets embedded applications, we focus on efficient uses of limited resources, especially the memory bandwidth. The designed accelerator can process the images of $640{\times}240$ pixels with moderate complexity at the rate of 30 frames per second.