• 산업경영시스템학회지
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• 제34권3호
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• pp.49-56
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• 2011

Estimating optimum hardware capacity of an e-learning system is very important process to grasp reasonable size of designing technique architecture and budget during step of ISP(information strategic planning) and development. It hugely influences cost and quality of the whole project. While investment on information system hardware has been continuously increased, there was no certified hardware capacity estimating method in e-learning system development. A guideline for hardware sizing of information systems was established by Telecommunication Technology Association in 2008. However, the guideline is not appropriate for estimating optimum hardware capacity of an e-learning system because it was designed to provide general standards for estimating hardware capacity of various types of projects. The purpose of this paper is to provide a methodology for estimating optimum hardware capacity in e-learning system development. To develop the methodology, this study, first of all, analyzes two e-learning development projects, in which the guideline was applied to estimate optimum hardware capacity. Then, this study finds out several key factors influencing on hardware capacity. Finally, this study suggests a methodology for estimating optimum hardware capacity of an e-learning system, in which weights for the factors are determined through AHP analysis.

• 디지털융복합연구
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• 제4권1호
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• pp.73-81
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• 2006

In this study, It is suggested how to utilize hardware capacity sizing system for WEB, WAS, OLTP server's CPU, memory, and disk capacity by its user reasonably. To achieve goal of this study, we presented specific approaches in aspect of institutional viewpoint. The result of this study can be reflected gradually in the guideline of informatization related budgeting by MPB(Ministry of Planning and Budget) and e-government supporting program.

• 한국디지털정책학회:학술대회논문집
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• 한국디지털정책학회 2006년도 춘계학술대회
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• pp.311-318
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• 2006

In this study, It is suggested how to utilize hardware capacity sizing system for WEB, WAS, OLTP server's CPU, memory, and disk capacity by its user reasonably. To achieve goal of this study, we presented specific approaches in aspect of institutional viewpoint. The result of this study can be reflected gradually in the guideline of informatization related budgeting by MPB(Ministry of Planning and Budget) and e-government supporting program.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권5호
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• pp.2357-2380
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• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.23-26
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• 2022

In this paper, our ray tracing hardware is implemented on the latest high-capacity FPGA board. The system included ray tracing hardware for rendering and tree building hardware for handling dynamic scenes. The FPGA board used in the implementation is a Xilinx Alveo U250 accelerator card for data centers. This included 12 ray tracing hardware cores and 1 tree-building hardware core. As a result of testing in various scenes in Full HD resolution, the FPS performance of the proposed ray tracing system was measured from 8 to 28. The overall average is about 17.7 FPS.

• 한국IT서비스학회지
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• 제5권1호
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• pp.47-59
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• 2006

According to the policy for "e-Korea construction" of Korean government, Investment of information system during the past decade are dramatically increasing. More than a half of this investment is cost of hardware infrastructure. So, accurate hardware sizing are essential for higher efficiency of investment. Accurate hardware sizing benefits are generally viewed in terms of the avoidance of excess equipment and lost opportunity costs by not being able to support business needs. Unfortunately, however, little research effort to make the hardware sizing methodology are doing. We propose a sizing method for information system in public sector. This method is determinate empirical study that are gathering and analyzing cases, making method and reviewing expert. Finally we are proposed calculating method for hardware components that is CPU, memory, internal and external disk according to the application system type which is OLTP, Web, WAS. Our study certainly will act as a catalyst for higher investment-efficiency of the future information programs in public sector.

• Journal of Power Electronics
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• 제10권5호
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• pp.555-562
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• 2010

This paper presents the development of a hardware simulator for a 3-parallel grid-connected PMSG wind power system. With the development of permanent magnetic materials in recent years, the capacity of a PMSG based wind turbine system, which requires a full-scale power converter, has been raised up to a few MW. Since it is limited by the available semiconductor technology, such large amounts of power cannot be delivered with only one power converter. Hence, a parallel connecting technique for converters is required to reduce the ratings of the converters. In this paper, a hardware simulator with 3-parallel converters is described and its control issues are presented as well. Some experimental results are given to illustrate the performance of the simulator system.

• 한국콘텐츠학회논문지
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• 제5권5호
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• pp.107-114
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• 2005

모바일 게임 환경은 하드웨어 폰(Phone)CPU처리 속도 향상, 3D 엔진 탑재, 가용량 메모리 확대 등으로 인하여 차세대 3D 모바일 게임 시장이 활발하게 떠오르고 있다. 최근 이러한 동향에 발맞추어 PS2(PlayStation2)나 온라인(Online)에서 인기를 얻은 3D 게임이 모바일 게임용으로 출시하고 있다. 그러나 모바일 환경은 PC, 콘솔(Console)등의 다른 플랫폼에 비해 하드웨어적 특성이 다르기 때문에 PC기반의 3D 게임을 작은 휴대폰으로 옮기는 것은 단말기의 배터리 용량, 디스플레이 크기의 한계, 게임 콘텐츠 용량, 다른UI(User Interface)등과 같이 휴대 단말기 차원에서의 제약을 받는다. 이러한 많은 제약 중에서 특히 게임 컨텐츠를 축소하여 저용량화 하기 위한 연구의 필요성이 대두되고 있으며, 3D 모바일 게임은 3D 캐릭터가 작은 모바일 화면에서 사실적이며 자유로운 애니메이션이 무엇보다 중요하다. 본 연구는 3D 모바일 게임에 적합하도록 저용량 3D 캐릭터 애니메이션의 제작에 관한 연구를 하였다.

• 한국IT서비스학회지
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• 제3권2호
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• pp.9-23
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• 2004

Interest about Information infrastructure construction is enlarged socially according to arrival of information age, and various information systems are constructed for efficient business processing, customer service in public sector. According to subjective method for performance improvement for information system of public sector and engine that propel information system construction because it is no definite hardware sizing guidelines for information system caterer, is calculating resource volume of information system. It is situation that problem of excess of scale or reduce sizing is happening and is causing various kind of problems that is waste of information budget and service decline thereby. In this research, we proposed hardware sizing framework for information system that is applied to pubic sector.

• 전자통신동향분석
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• 제37권1호
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.