• Journal of Korean Society of Industrial and Systems Engineering
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• v.34 no.3
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• pp.49-56
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• 2011

Estimating optimum hardware capacity of an e-learning system is very important process to grasp reasonable size of designing technique architecture and budget during step of ISP(information strategic planning) and development. It hugely influences cost and quality of the whole project. While investment on information system hardware has been continuously increased, there was no certified hardware capacity estimating method in e-learning system development. A guideline for hardware sizing of information systems was established by Telecommunication Technology Association in 2008. However, the guideline is not appropriate for estimating optimum hardware capacity of an e-learning system because it was designed to provide general standards for estimating hardware capacity of various types of projects. The purpose of this paper is to provide a methodology for estimating optimum hardware capacity in e-learning system development. To develop the methodology, this study, first of all, analyzes two e-learning development projects, in which the guideline was applied to estimate optimum hardware capacity. Then, this study finds out several key factors influencing on hardware capacity. Finally, this study suggests a methodology for estimating optimum hardware capacity of an e-learning system, in which weights for the factors are determined through AHP analysis.

• Journal of Digital Convergence
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• v.4 no.1
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• pp.73-81
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• 2006

In this study, It is suggested how to utilize hardware capacity sizing system for WEB, WAS, OLTP server's CPU, memory, and disk capacity by its user reasonably. To achieve goal of this study, we presented specific approaches in aspect of institutional viewpoint. The result of this study can be reflected gradually in the guideline of informatization related budgeting by MPB(Ministry of Planning and Budget) and e-government supporting program.

• 한국디지털정책학회:학술대회논문집
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• 2006.06a
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• pp.311-318
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• 2006

In this study, It is suggested how to utilize hardware capacity sizing system for WEB, WAS, OLTP server's CPU, memory, and disk capacity by its user reasonably. To achieve goal of this study, we presented specific approaches in aspect of institutional viewpoint. The result of this study can be reflected gradually in the guideline of informatization related budgeting by MPB(Ministry of Planning and Budget) and e-government supporting program.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.5
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• pp.2357-2380
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• 2019

In this paper, we investigate the impact of hardware impairments (HWIs) on the performance of a downlink massive MIMO system. We consider a single-cell system with maximum ratio transmission (MRT) as precoding scheme, and with all the HWIs characteristics such as phase noise, distortion noise, and amplified thermal noise. Based on the system model, we derive closed-form expressions for a typical user data rate under two scenarios: when a common local oscillator (CLO) is used at the base station and when separated oscillators (SLOs) are used. We also derive closed-form expressions for the downlink transmit power required for some desired per-user data rate under each scenario. Compared to the conventional system with ideal transceiver hardware, our results show that impairments of hardware make a finite upper limit on the user's downlink channel capacity; and as the number of base station antennas grows large, it is only the hardware impairments at the users that mainly limit the capacity. Our results also show that SLOs configuration provides higher data rate than CLO at the price of higher power consumption. An approach to minimize the effect of the hardware impairments on the system performance is also proposed in the paper. In our approach, we show that by reducing the cell size, the effect of accumulated phase noise during channel estimation time is minimized and hence the user capacity is increased, and the downlink transmit power is decreased.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.23-26
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• 2022

In this paper, our ray tracing hardware is implemented on the latest high-capacity FPGA board. The system included ray tracing hardware for rendering and tree building hardware for handling dynamic scenes. The FPGA board used in the implementation is a Xilinx Alveo U250 accelerator card for data centers. This included 12 ray tracing hardware cores and 1 tree-building hardware core. As a result of testing in various scenes in Full HD resolution, the FPS performance of the proposed ray tracing system was measured from 8 to 28. The overall average is about 17.7 FPS.

• Journal of Information Technology Services
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• v.5 no.1
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• pp.47-59
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• 2006

According to the policy for "e-Korea construction" of Korean government, Investment of information system during the past decade are dramatically increasing. More than a half of this investment is cost of hardware infrastructure. So, accurate hardware sizing are essential for higher efficiency of investment. Accurate hardware sizing benefits are generally viewed in terms of the avoidance of excess equipment and lost opportunity costs by not being able to support business needs. Unfortunately, however, little research effort to make the hardware sizing methodology are doing. We propose a sizing method for information system in public sector. This method is determinate empirical study that are gathering and analyzing cases, making method and reviewing expert. Finally we are proposed calculating method for hardware components that is CPU, memory, internal and external disk according to the application system type which is OLTP, Web, WAS. Our study certainly will act as a catalyst for higher investment-efficiency of the future information programs in public sector.

• Journal of Power Electronics
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• v.10 no.5
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• pp.555-562
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• 2010

This paper presents the development of a hardware simulator for a 3-parallel grid-connected PMSG wind power system. With the development of permanent magnetic materials in recent years, the capacity of a PMSG based wind turbine system, which requires a full-scale power converter, has been raised up to a few MW. Since it is limited by the available semiconductor technology, such large amounts of power cannot be delivered with only one power converter. Hence, a parallel connecting technique for converters is required to reduce the ratings of the converters. In this paper, a hardware simulator with 3-parallel converters is described and its control issues are presented as well. Some experimental results are given to illustrate the performance of the simulator system.

• The Journal of the Korea Contents Association
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• v.5 no.5
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• pp.107-114
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• 2005

The next generation of 3D mobile games market is becoming increasingly active, more as a result of improvement in the CPU speed of hardware phone, embarkation of 3D engines and high memory capacity, In response to this trend, popular 3D games of PS2 (PlayStation2) and popular online games are being launched as mobile games. However, mobile units have different hardware characteristics compared to those of other platforms such as the PC or the game console. Therefore, mobile game versions of the popular PC games face many limitations in many aspects such as in battery capacity, size of display, capacity of the game, and other user interface issues. Among these many limitations, study for allowing low capacity storage of the game is becoming important. In addition, realistic animation of the 3D character on the small screen of the mobile unit is more important than any other matter. The purpose of this study is to find a solution to providing realistic 3D character animation, and for decreasing the storage capacity of character animation for application in 3D mobile games.

• Journal of Information Technology Services
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• v.3 no.2
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• pp.9-23
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• 2004

Interest about Information infrastructure construction is enlarged socially according to arrival of information age, and various information systems are constructed for efficient business processing, customer service in public sector. According to subjective method for performance improvement for information system of public sector and engine that propel information system construction because it is no definite hardware sizing guidelines for information system caterer, is calculating resource volume of information system. It is situation that problem of excess of scale or reduce sizing is happening and is causing various kind of problems that is waste of information budget and service decline thereby. In this research, we proposed hardware sizing framework for information system that is applied to pubic sector.

• Electronics and Telecommunications Trends
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• v.37 no.1
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• pp.42-52
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• 2022

With the advent of the big data era, the memory capacity required for computing systems is rapidly increasing, especially in High Performance Computing systems. However, the number of DRAMs that can be used in a computing node is limited by the structural limitations of the hardware (for example, CPU specifications). Memory expansion technology has attracted attention as a means of overcoming this limitation. This technology expands the memory capacity by leveraging the external memory connected to the host system through hardware interface such as PCIe and CCIX. In this paper, we present an overview and describe the development trends of the memory expansion technology. We also provide detailed descriptions and use cases of the CCIX that provides higher bandwidth and lower latency than cases of the PCIe.