• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
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• pp.149-152
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• 2000

In the Internet, multimedia data transfer is hard to guarantee the characteristics of the Real-Time because of the Best-Effort of the nature of IP, then additional mechanism is applied to multimedia application for real-time data. In this paper, we introduce the nature of multimedia and the necessary facility for real-time protocol. We propose protocol layer, which has necessary function above mentioned and offer the end-to-end transfer far real-time data. Also, the proposed protocol perform a next low operation: 1) a required information for QoS control by using Feedback mechanism is obtained from sender, 2) divided a transferred packet by delay and loss priority. 3) recognized the low service models, and 4) decided a bandwidth and QoS according to a network state

• 한국정보과학회논문지:소프트웨어및응용
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• 제28권12호
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• pp.921-929
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• 2001

PCL(Object Constraint Language)은 UML, 메타모델을 정밀하게 명세화하기 위해서 UML 의미론의 도큐먼트에 사용되어졌다. 피리고 UMLl-은 실시간 UML 웹 개발 UML 등과 같이 다양한 시스템을 개발하기 위해서 확장되었다. 특히 실시간 시스템을 개발할 때 적시성, 동시성, 예측성, 신뢰성이 고려되어야 한다 이에 따라 실시간 UML을 정밀하게 표현하고 구현을 쉽게 하기 위해서 OCL을 사용해야 하지만 현재의 OCL로 실시간을 묘사하기에는 부적합하다. 본 논문에서는 실시간 시스템을 개발하는데 있어서 실시간 언어고 쉽게 변환이 가능하도록 이벤트 위주로 실시간 OCL을 제안하였고 그 효용성의 검증으로서 권선기 시뮬레이터 개발에 응용하였다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제9권2호
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• pp.94-98
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• 2009

This paper proposes an architecture of a real-time EtherCAT master library called RtEML. The controls EtherCAT slaves under EtherCAT protocol in real-time. It provides a simple programming interface which is useful in developing robot application in C/C++ or C#. To achieve deterministic, hard real-time control in Microsoft Windows environment without additional hardware, INtime is used. Since INtime is designed specifically to take advantage of the powerful capabilities of the x86 processor architecture, the proposed RtEML achieves microseconds of real-time performance.

• Journal of Electrical Engineering and information Science
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• 제1권1호
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• pp.118-128
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• 1996

In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

• Journal of Computing Science and Engineering
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• 제9권4호
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• pp.177-189
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• 2015

High-performance processors using Non-Uniform Cache Architecture (NUCA) are increasingly used to deal with the growing wire delays in multicore/manycore processors. Due to the convergence of high-performance computing with embedded computing, NUCA caches are expected to benefit high-end embedded systems as well. However, for real-time systems that use multicore processors with NUCA caches, it is crucial to bound worst-case execution time (WCET) accurately and safely. In this paper, we developed a WCET analysis approach by considering the effect of static NUCA caches on WCET. We compared the WCET in real-time applications with different topologies of static NUCA caches. Our experimental results demonstrated that the static NUCA cache could improve the worst-case performance of realtime applications using multicore processor compared to the cache with uniform access time.

• 대한전자공학회논문지
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• 제26권10호
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• pp.1518-1527
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• 1989

We proposed a technique to design a multimicrocomputer system for real-time parallel processing with an interconnection network which has good network latency time. In order to simplify the performance evaluation and the design procedure under the hard real-time constraints we defined network latency time which takes into account the queueing delays of the networks. We designed a dynamic interconnection network following the proposed technique, and the simulation results show that we can easily estimate the multimicrocomputer system's approximate performance using the defined network latency time before the actual design, so this definition can help the efficient design of the real-time parallel processing systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.109-112
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• 1997

A Discrete Event Dynamic System is a system whose states change in response to the occurrence of events from a predefined event set. A major difficulty in developing analytical results for the systems is the lack of appropriate modeling techniques. This paper proposes the use of Real-time Temporal Logic as a modeling tool for the modeling and control of fixed-time traffic control problem which by way of a DEDS. The Real-time Temporal Logic Frameworks is extended with a suitable structure of modeling hard real-time constraints. Modeling rules are developed for several specific situations. It is shown how the graphical model can be translated to a system of linear equations and constraints.

• International Journal of Aeronautical and Space Sciences
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• 제17권1호
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• pp.37-44
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• 2016

Optical fiber temperature sensing systems have incomparable advantages over traditional electrical-cable-based monitoring systems. However, the fiber optic interrogators and sensors have often been rejected as a temperature monitoring technology in real-world industrial applications because of high cost and over-specification. This study proposes a multiplexed fiber optic temperature monitoring sensor system using an economical Optical Time-Domain Reflectometer (OTDR) and Hard-Polymer-Clad Fiber (HPCF). HPCF is a special optical fiber in which a hard polymer cladding made of fluoroacrylate acts as a protective coating for an inner silica core. An OTDR is an optical loss measurement system that provides optical loss and event distance measurement in real time. A temperature sensor array with the five sensor nodes at 10-m interval was economically and quickly made by locally stripping HPCF clad through photo-thermal and photo-chemical processes using a continuous/pulse hybrid-mode laser. The exposed cores created backscattering signals in the OTDR attenuation trace. It was demonstrated that the backscattering peaks were independently sensitive to temperature variation. Since the 1.5-mm-long exposed core showed a 5-m-wide backscattering peak, the OTDR with a spatial resolution of 40 mm allows for making a sensor node at every 5 m for independent multiplexing. The performance of the sensor node included an operating range of up to $120^{\circ}C$, a resolution of $0.59^{\circ}C$, and a temperature sensitivity of $-0.00967dB/^{\circ}C$. Temperature monitoring errors in the environment tests stood at $0.76^{\circ}C$ and $0.36^{\circ}C$ under the temperature variation of the unstrapped fiber region and the vibration of the sensor node. The small sensitivities to the environment and the economic feasibility of the highly multiplexed HPCF temperature monitoring sensor system will be important advantages for use as system-integrated temperature sensors.

• 한국정보과학회논문지:정보통신
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• 제32권5호
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• pp.633-640
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• 2005

본 논문은 이중 IEEE 802.11 무선 근거리 통신망 상에서의 경성 실시간 통신을 위한 메시지 스케줄링 기법과 이에 따르는 대역폭 할당 기법을 제안하고 그 성능을 분석한다. 동일한 주기를 갖는 각 네트워크에서 슈퍼프레임이 서로 반주기의 편차를 갖고 진행되도록 함으로써 최대 대기시간을 반으로 감소시키고 비콘 지연 현상이 실시간 트래픽 스케줄링에 주는 영향을 최소화한다. 비콘 지연 현상의 영향이 오프라인시에 형식화되고 고려되어 라운드로빈 방식을 기반으로 PCF 구간의 폴링 스케줄을 결정한다. ns-2에의해 수행된 모의실험은 제안된 방식이 실험을 위해 생성된 메시지 집합에 있어서 동일한 대역폭과 MAC 방식을 갖는 이중 근거리 통신망에 비하여 실시간 메시지의 스케줄가능성을 $36\%$ 향상시킬 수 있으며 비실시간 메시지들에게는 $9\%$의 대역폭을 더 할당할 수 있음을 보인다.

• Journal of Computing Science and Engineering
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• 제6권1호
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• pp.26-38
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• 2012

Java has been increasingly used in programming for real-time systems. However, some of Java's features such as automatic memory management and dynamic compilation are harmful to time predictability. If these problems are not solved properly then it can fundamentally limit the usage of Java for real-time systems, especially for hard real-time systems that require very high time predictability. In this paper, we propose to exploit multicore computing in order to reduce the timing unpredictability that is caused by dynamic compilation and adaptive optimization. Our goal is to retain high performance comparable to that of traditional dynamic compilation, while at the same time, obtain better time predictability for Java virtual machine (JVM). We have studied pre-compilation techniques to utilize another core more efficiently, preoptimization on another core (PoAC) scheme to replace the adaptive optimization system (AOS) in Jikes JVM and the counter based optimization (CBO). Our evaluation reveals that the proposed approaches are able to attain high performance while greatly reducing the variation of the execution time for Java applications.