• Title/Summary/Keyword: Hard real-time

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Dynamic QoS Control Algorithm of Real-time Transfer Protocol based on Delay and Loss Priority (지연과 손실우선순위에 따른 실시간 멀티미디어 전송 프로토콜의 동적 QoS 제어 알고리즘)

  • 김정철;이성섭;김체훤;남지승
    • Proceedings of the IEEK Conference
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    • 2000.06c
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    • pp.149-152
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    • 2000
  • In the Internet, multimedia data transfer is hard to guarantee the characteristics of the Real-Time because of the Best-Effort of the nature of IP, then additional mechanism is applied to multimedia application for real-time data. In this paper, we introduce the nature of multimedia and the necessary facility for real-time protocol. We propose protocol layer, which has necessary function above mentioned and offer the end-to-end transfer far real-time data. Also, the proposed protocol perform a next low operation: 1) a required information for QoS control by using Feedback mechanism is obtained from sender, 2) divided a transferred packet by delay and loss priority. 3) recognized the low service models, and 4) decided a bandwidth and QoS according to a network state

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An Event-Driven Real-Time OCL and Its Application (이벤트 위주의 실시간 OCL과 그 응용)

  • Choi, Sung-Woon;Lee, Young-Whan
    • Journal of KIISE:Software and Applications
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    • v.28 no.12
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    • pp.921-929
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    • 2001
  • OCL was used in the UML Semantics document to specify the well-formedness rules of the UML metarmodel. UML was extended to apply it to system developments of several fields, for example real-time UML and web applications with UML. In particular the dependability is important in designing and building hard real-time system. Thus OCL is needed to express real-time UML formally and so it must extended. In this paper, we extend OCL to define event-driven real-time OCL to the development of Nrcl simulator.

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Development of Realtime EtherCAT Master Library Using INtime

  • Moon, Yong-Seon;Trong, Tuan Anh Vo;Ko, Nak-Yong;Seo, Dong-Jin;Lim, Seung-Woo
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.9 no.2
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    • pp.94-98
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    • 2009
  • This paper proposes an architecture of a real-time EtherCAT master library called RtEML. The controls EtherCAT slaves under EtherCAT protocol in real-time. It provides a simple programming interface which is useful in developing robot application in C/C++ or C#. To achieve deterministic, hard real-time control in Microsoft Windows environment without additional hardware, INtime is used. Since INtime is designed specifically to take advantage of the powerful capabilities of the x86 processor architecture, the proposed RtEML achieves microseconds of real-time performance.

Fine-Grain Real-Time Code Scheduling for VLIW Architecture

  • Chung, Tai M.;Hwang, Dae J.
    • Journal of Electrical Engineering and information Science
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    • v.1 no.1
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    • pp.118-128
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    • 1996
  • In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

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Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing

  • Ding, Yiqiang;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.9 no.4
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    • pp.177-189
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    • 2015
  • High-performance processors using Non-Uniform Cache Architecture (NUCA) are increasingly used to deal with the growing wire delays in multicore/manycore processors. Due to the convergence of high-performance computing with embedded computing, NUCA caches are expected to benefit high-end embedded systems as well. However, for real-time systems that use multicore processors with NUCA caches, it is crucial to bound worst-case execution time (WCET) accurately and safely. In this paper, we developed a WCET analysis approach by considering the effect of static NUCA caches on WCET. We compared the WCET in real-time applications with different topologies of static NUCA caches. Our experimental results demonstrated that the static NUCA cache could improve the worst-case performance of realtime applications using multicore processor compared to the cache with uniform access time.

Multimicrocomputer Network Design for Real-Time Parallel Processing (실시간 병렬처리를 위한 다중마이크로컴퓨터망의 설계)

  • 김진호;고광식;김항준;최흥문
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.10
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    • pp.1518-1527
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    • 1989
  • We proposed a technique to design a multimicrocomputer system for real-time parallel processing with an interconnection network which has good network latency time. In order to simplify the performance evaluation and the design procedure under the hard real-time constraints we defined network latency time which takes into account the queueing delays of the networks. We designed a dynamic interconnection network following the proposed technique, and the simulation results show that we can easily estimate the multimicrocomputer system's approximate performance using the defined network latency time before the actual design, so this definition can help the efficient design of the real-time parallel processing systems.

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Modeling and Control of Fixed-time Traffic Control Problem with Real-time Temporal Logic Frameworks (실시간 시간논리구조를 이용한 고정시간 교통제어 문제의 모델링 및 제어)

  • Jeong, Yong-Man;Lee, Won-Hyok;Choi, Jeong-Nae;Hwang, Hyung-Soo
    • Proceedings of the KIEE Conference
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    • 1997.11a
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    • pp.109-112
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    • 1997
  • A Discrete Event Dynamic System is a system whose states change in response to the occurrence of events from a predefined event set. A major difficulty in developing analytical results for the systems is the lack of appropriate modeling techniques. This paper proposes the use of Real-time Temporal Logic as a modeling tool for the modeling and control of fixed-time traffic control problem which by way of a DEDS. The Real-time Temporal Logic Frameworks is extended with a suitable structure of modeling hard real-time constraints. Modeling rules are developed for several specific situations. It is shown how the graphical model can be translated to a system of linear equations and constraints.

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Multiplexed Hard-Polymer-Clad Fiber Temperature Sensor Using An Optical Time-Domain Reflectometer

  • Lee, Jung-Ryul;Kim, Hyeng-Cheol
    • International Journal of Aeronautical and Space Sciences
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    • v.17 no.1
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    • pp.37-44
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    • 2016
  • Optical fiber temperature sensing systems have incomparable advantages over traditional electrical-cable-based monitoring systems. However, the fiber optic interrogators and sensors have often been rejected as a temperature monitoring technology in real-world industrial applications because of high cost and over-specification. This study proposes a multiplexed fiber optic temperature monitoring sensor system using an economical Optical Time-Domain Reflectometer (OTDR) and Hard-Polymer-Clad Fiber (HPCF). HPCF is a special optical fiber in which a hard polymer cladding made of fluoroacrylate acts as a protective coating for an inner silica core. An OTDR is an optical loss measurement system that provides optical loss and event distance measurement in real time. A temperature sensor array with the five sensor nodes at 10-m interval was economically and quickly made by locally stripping HPCF clad through photo-thermal and photo-chemical processes using a continuous/pulse hybrid-mode laser. The exposed cores created backscattering signals in the OTDR attenuation trace. It was demonstrated that the backscattering peaks were independently sensitive to temperature variation. Since the 1.5-mm-long exposed core showed a 5-m-wide backscattering peak, the OTDR with a spatial resolution of 40 mm allows for making a sensor node at every 5 m for independent multiplexing. The performance of the sensor node included an operating range of up to $120^{\circ}C$, a resolution of $0.59^{\circ}C$, and a temperature sensitivity of $-0.00967dB/^{\circ}C$. Temperature monitoring errors in the environment tests stood at $0.76^{\circ}C$ and $0.36^{\circ}C$ under the temperature variation of the unstrapped fiber region and the vibration of the sensor node. The small sensitivities to the environment and the economic feasibility of the highly multiplexed HPCF temperature monitoring sensor system will be important advantages for use as system-integrated temperature sensors.

A New Bandwidth Allocation Scheme for Hard Real-time Communication on Dual IEEE 802.11 WLANs (이중 IEEE 802.11 WLAN에서 경성 실시간 통신을 위한 대역폭 할당)

  • Lee, Jung-Hoon;Kang, Mi-Kyung
    • Journal of KIISE:Information Networking
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    • v.32 no.5
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    • pp.633-640
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    • 2005
  • This paper proposes and analyzes a message scheduling scheme and corresponding bandwidth allocation method for the hard real-time communication on dual standard 802.11 Wireless LANs. By making the superframeof one network precede that of the other by half, the dual network architecture can minimize the effect of deferred beacon and reduce the worst case waiting timeby half. The effect of deferred beacon is formalized and directly considered to decide the polling schedule of PCF phase. Simulation results executed via ns-2 show that the proposed scheme can improve the schedulability by 3$36\%$ for real-time messages and give $9\%$ more bandwidth to non-real-time messages for the given stream sets, compared with the network whose bandwidth is just doubled with the same MAC.

Time-Predictable Java Dynamic Compilation on Multicore Processors

  • Sun, Yu;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.6 no.1
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    • pp.26-38
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    • 2012
  • Java has been increasingly used in programming for real-time systems. However, some of Java's features such as automatic memory management and dynamic compilation are harmful to time predictability. If these problems are not solved properly then it can fundamentally limit the usage of Java for real-time systems, especially for hard real-time systems that require very high time predictability. In this paper, we propose to exploit multicore computing in order to reduce the timing unpredictability that is caused by dynamic compilation and adaptive optimization. Our goal is to retain high performance comparable to that of traditional dynamic compilation, while at the same time, obtain better time predictability for Java virtual machine (JVM). We have studied pre-compilation techniques to utilize another core more efficiently, preoptimization on another core (PoAC) scheme to replace the adaptive optimization system (AOS) in Jikes JVM and the counter based optimization (CBO). Our evaluation reveals that the proposed approaches are able to attain high performance while greatly reducing the variation of the execution time for Java applications.