• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.917-924
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• 2008

Motion estimation and compensation in the spatial domain check the searching area of specified size in the previous frame and search block to minimize the difference with current block. When we check the searching area, it consumes the most encoding times due to increasing the complexity. We can solve this fault by means of motion estimation using shifting matrix in the transform domain instead of the spatial domain. We derive so the existed shifting matrix to a new recursion equation that we decrease more computations. We modify simply vertical shifting matrix and horizontal shifting matrix in the transform domain for motion estimation of half-pixel accuracy. So, we solve increasing computation due to bilinear interpolation in the spatial domain. Simulation results prove that motion estimation by the proposed algorithm in DCT-based transform domain provides higher PSNR using fewer bits than results in the spatial domain.

• Investigative Magnetic Resonance Imaging
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• v.1 no.1
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• pp.114-118
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• 1997

Purpose: Functional MR imaging is the method of demonstrating changes in regional cerebral blood flow produced by sensory, motor, and any other tasks. Functional MR of visual cortex is performed as a patient stares a photic stimulation, so adaptable photic stimulation is necessary. The purpose of this study is to evaluate whether the size of photic stimulator can affect the degree of visual cortex activation. Materials and Methods: Functional MR imaging was performed in 5 volunteers with normal visual acuity. Photic stimulator was made by 39 light-emitting diodes on a plate, operating at 8Hz. The sizes of photic stimulator were full field, half field and focal central field. The MR imager was Siemens 1.5-T Magnetom Vision system, using standard head coil. Functional MRI utilized EPI sequence (TR/TE= 1.0/51. Omsec, matrix $No.=98{\times}128$, slice thickness=8mm) with 3sets of 6 imaging during stimulation and 6 imaging during rest, all 36 scannings were obtained. Activation images were obtained using postprocessing software(statistical analysis by Z-score), and these images were combined with T-1 weighted anatomical images. The activated signals were quantified by numbering the activated pixels, and activation a index was obtained by dividing the pixel number of each stimulator size with the sum of the pixel number of 3 study using 3 kinds of stimulators. The correlation between the activation index and the stimulator size was analysed. Results: Mean increase of signal intensities on the activation area using full field photic stimulator was about 9.6%. The activation index was greatest on full field, second on half field and smallest on focal central field in 4. The index of half field was greater than that of full field in 1. The ranges of activation index were full field 43-73%(mean 55%), half field 22-40 %(mean 32%), and focal central field 5-24%(mean 13%). Conclusion: The degree of visual cortex activation increases with the size of photic stimulator.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.71-75
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• 2019

This paper proposes the extension of the dynamic range in complementary metal oxide semiconductor (CMOS) image sensors (CIS) using switching operation of in-pixel inverter. A CMOS inverter is integrated in each unit pixel of the proposed CIS for switching operations. The n+/p-substrate photodiode junction capacitances are added to each unit pixel. When the output voltage of the photodiode is less than half of the power supply voltage of the CMOS inverter, the output voltage of the CMOS inverter changes from 0 V to the power supply voltage. Hence, the output voltage of the CMOS inverter is adjusted by changing the supply voltage of the CMOS inverter. Thus, the switching point is adjusted according to light intensity when the supply voltage of the CMOS inverter changes. Switching operations are then performed because the CMOS inverter is integrated with in each unit pixel. The proposed CIS is composed of a pixel array, multiplexers, shift registers, and biasing circuits. The size of the proposed pixel is $10{\mu}m{\times}10{\mu}m$. The number of pixels is $150(H){\times}220(V)$. The proposed CIS was fabricated using a $0.18{\mu}m$ 1-poly 6-metal CMOS standard process and its characteristics were experimentally analyzed.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.543-550
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• 2000

An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.05a
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• pp.463-466
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• 2005

While recent display devices are becoming light and slim, the size of a screen is especially the important issue in the field of display devices. Furthermore, it is also required that the projection TV, a large screen display device, be able to represent higher resolutions as the digital broadcasting is set off. In order to realize high resolutions in a DLP projection TV, the number of pixel on DMD should be increased. However, a large number of pixels make it difficult to realize resulting small sized pixels and this cause the increase in cost. Therefore, we propose a simple and improved pixel enhancement actuator using the existing DMD by offsetting half pixels repeatedly in the vertical direction.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.1
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• pp.93.2-93.2
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• 2012

Point Spread Function (PSF) is one of the most important optical characteristics for describing the performance of a telescope. And a concept of subpixelization is inevitable in evaluating the undersampled PSF (Shin and Sakurai 2009). Then, the internal structure of Yohkoh SXT CCD pixel is not uniform: For the top half of pixel area, the X-ray should pass a so-called gate structure where the charges are transferred to an output amplifier. This gate structure shows energy-dependent sensitivity (Tsuneta et al. 1991). For example, for Al-K (8.34 A) X-ray emission, the transmission of the polysilicon gate is about 0.9. Also, for the peak coronal response of the SXT thin filters, around 17 angstrom (0.729 keV), the transmission of the gate is about 0.6, falling off sharply towards longer wavelengths. It should be noted that this spectrally dependent non-uniform response of each CCD pixel will certainly have a noticeable effect on the properties of the PSF at longer wavelengths. Therefore, especially for analyzing the undersampled PSF of low energy source, a careful consideration of non-uniform internal pixel structure is required in determining the shape of the PSF core. The details on the effect of gate structure will be introduced in our presentation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• International Journal of Computer Science & Network Security
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• v.23 no.4
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• pp.85-94
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• 2023

Image halftoning is a technique for varying grayscale images into two-tone binary images. Unfortunately, the static representation of an image-half toning, wherever each pixel intensity is combined by its local neighbors only, causes missing subjective problem. Also, the existing noise causes an instability criterion. In this paper an image half-toning is represented as a dynamical system for recognizing the global representation. Also, noise is reduced based on a probabilistic model. Since image half-toning is considered as 2-D matrix with a full connected pass, this structure is recognized by the dynamical system of Cellular Neural Networks (CNNs) which is defined by its template. Bayesian Rough Sets is used in exploiting the ideal CNNs construction that synthesis its dynamic. Also, Bayesian rough sets contribute to enhance the quality of the halftone image by removing noise and discovering the effective parameters in the CNNs template. The novelty of this method lies in finding a probabilistic based technique to discover the term of CNNs template and define new learning rules for CNNs internal work. A numerical experiment is conducted on image half-toning corrupted by Gaussian noise.

• ETRI Journal
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• v.22 no.1
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.321-326
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• 2017

High Efficiency Video Coding (HEVC) adopted the Discrete Cosine Transform-II (DCT-II) based interpolation filter to improve coding efficiency in motion compensation and estimation. In HEVC, the interpolation filters based on the DCT-II are composed of 8-point for half-pixel and 7-point for 1/4-pixel and 3/4-pixel. In this paper, a DST-VII based interpolation filter is used improve motion compensation and estimation. The experimental results which applied the DST-VII interpolation filter are presented. They show the 0.45% of average bitrate reduction in Random Access configuration and 0.5% of average bitrate reduction in Low Delay B configuration, respectively.