• Title/Summary/Keyword: HD video

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Real-time Video Auto White Balance Algorithm Implementation for HD IP Network Camera based on DM36x (DM36x 기반 HD IP 네트워크 카메라를 위한 실시간 비디오 자동 백색 보정 알고리즘 구현)

  • Choi, Kwon-Seok;Chung, Sun-Tae;Kang, Ho-Seok
    • Proceedings of the Korea Multimedia Society Conference
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    • 2012.05a
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    • pp.18-21
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    • 2012
  • 자동 백색 보정은 디지털 비디오 프로세싱에서 매우 중요한 기능이며, IP 네트워크 카메라의 경우에도 필수적인 영상 전처리 과정이다. 본 논문은 TI 사의 비디오 프로세서인 DM36x을 이용하여 제작된 HD IP 네트워크 카메라에서의 실시간으로 동작할 수 있는 효과적인 비디오 자동 백색 보정 알고리즘을 구현한 결과를 기술한다. 구현한 자동 백색 보정 알고리즘은 매우 효과적인 것으로 알려진 그레이 컬러 포인트 기반 알고리즘을 DM36x의 AWB 엔진이 제공하는 기능을 이용하여 실시간으로 동작될 수 있도록 고쳐서 구현하였다.

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Accelerating the Retinex Algorithm with CUDA

  • Seo, Hyo-Seok;Kwon, Oh-Young
    • Journal of information and communication convergence engineering
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    • v.8 no.3
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    • pp.323-327
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    • 2010
  • Recently, the television market trend is change to HD television and the need of the study on HD image enhancement is increased rapidly. To enhancement of image quality, the retinex algorithm is commonly used. That's why we studied how to accelerate the retinex algorithm with CUDA on GPGPU (general purpose graphics processing unit). Calculating average part in retinex algorithm is similar to pyramidal calculation. We parallelize this recursive pyramidal average calculating for all layers, map the average data into the 2D plane and reduce the calculating time dramatically. Sequential C code takes 8948ms to get the average values for all layers in $1024{\times}1024$ image, but proposed method takes only only about 0.9ms for the same image. We are going to study about the real-time HD video rendering and image enhancement.

A Car Black Box Video Data Integrity Assurance Scheme Using Cyclic Data Block Chaining (순환형 데이터 블록 체이닝을 이용한 차량용 블랙박스의 영상 데이터 무결성 보장 기법)

  • Yi, Kang;Kim, Kyung-Mi;Cho, Yong Jun
    • Journal of KIISE
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    • v.41 no.11
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    • pp.982-991
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    • 2014
  • The integrity assurance of recorded video by car black boxes are necessary as the car black box is becoming more popular. In this paper, we propose a video data integrity assurance scheme reflecting the features of car black box. The proposed method can detect any kind of deletion, insertion, modification of frames by cyclic chaining using inter block relation. And, it provides the integrity assurance function consistently even in cases of file overwriting because of no more free space in storage, partial file data lost. And non-repudiation is supported. Experimental results with a car black box embedded system with A8 application processor show that our method has a feasible computational overhead to process full HD resolution video at 30 frames per second in a real time.

A Design of HD-SDI Camera System for HDcctv Standard Certification (HDcctv 표준 인증을 충족하는 HD-SDI 영상카메라의 설계)

  • Han, Byung-Wan;Lim, Sung-Jun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.6
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    • pp.2743-2750
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    • 2012
  • The SDI technology can transmit video, audio and control data with a coaxial cable. The compatibility of HD-SDI Camera is very important. The SDI devices and products without compliance problem are able to guarantee interaction. The HDcctv Alliance has released the standard by classifying the attributes of the SDI devices and products. It is important for each SDI devices and products to keep the compatibility of this standard. In this paper, the camera system that comply with the HDcctv Standard was implemented. In order to receive certification of HDcctv Alliance, the experiment was performed and the satisfied result was gained.

A hardware design of Rate control algorithm for H.264 (H.264 율제어 알고리듬의 하드웨어 설계)

  • Suh, Ki-Bum
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.1
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    • pp.175-181
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    • 2010
  • In this paper, we propose a novel hardware architecture for Rate control module for real time full HD video compression. In the proposed architecture, QP is updated by using the rate control algorithm to every the macroblock line(120MB for Full HD, 20MB for CIF image). Since there are many complex arithmetic and floating point arithmetic in rate control algorithm of JM for H.264, it is impossible to process the rate control algorithm using the integer arithmetic CPU core. So we adopted floating point arithmetic unit in our architecture, and implemented the rate control algorithm using the floating unit. With this implemented hardware, the implemented hardware is verified to be operated in real time.

A High-Performance and Low-Cost Histogram Equalization Scheme for Full HD Image (Full HD 비디오를 위한 고성능, 저비용 히스토그램 평활화 방법)

  • Choi, Jung-Hwan;Park, Jong-Sik;Lee, Seong-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.5
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    • pp.1147-1154
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    • 2011
  • Auto exposure (AE) in image signal processor (ISP) controls brightness of input image to the proper brightness when it is too dark or bright. But conventional AEs often fail to get proper brightness since AE controls only average brightness of image. Especially in applications that require object recognition, it cannot be solved the problem by AE of ISP. In this paper proposes Histogram Equalization (HE) processes that is the alternative of AE. It also proposes proper method to realize hardware and compensate HE problems conventional by using simple calculation.

A Bus Data Compression Method on a Phase-Based On-Chip Bus

  • Lee, Jae-Sung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.117-126
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    • 2012
  • This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

Overview and Performance analysis of the HEVC based Scalable Video Coding (HEVC 기반 스케일러블 비디오 부호화의 개요 및 성능 분석)

  • Choi, Jinhyuk;Choi, Haechul
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2013.11a
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    • pp.190-192
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    • 2013
  • 최근 HD(High Definition)화질 및 UHD(Ultra High Definition)화질과 같은 고품질 방송 서비스가 등장하고, 무선 네트워크 기술의 발달로 스마트폰, 태블릿PC 등과 같은 다양한 휴대용 멀티미디어 기기들이 존재함에 따라, 소비자들은 다양한 환경에서 고해상도 영상을 고품질로 사용하기를 원하고 있다. 따라서 스케일러빌러티의 현실적 필요성이 점점 대두되고 있으며, 이에 따라 ISO/IEC의 MPEG(Moving Picture Experts Group)와 ITU-T의 VCEG(Video Coding Experts Group)이 공동으로 결성한 Joint Collaborative Team on Video Coding(JCT-VC)에 의해 시간, 공간, 화질 등이 확장성을 제공하는 Scalable Video Coding(SVC)의 표준화가 진행되고 있다. 이에 본 논문은 공간적, 시간적, 화질적 스케일러빌러티(Scalability)를 제공하기 위한 SHVC의 표준 기술들에 대해 설명하고, 기존 단일 계층 부호화 방식(Single Video Coding)으로 서로 다른 해상도의영상을 Simulcast부호화한 결과와 비교하여 SHVC의 부호화한 결과와 비교하여 SHVC의 보호화 효율에 대한 성능을 분석 하였다.

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Cross-layered Video Information Sharing Method and Selective Retransmission Technique for The Efficient Video Streaming Services (효율적인 영상 스트리밍 서비스를 위한 Cross-layer 영상 정보 공유 방법 및 선택적 재전송 기법)

  • Chung, Taewook;Chung, Chulho;Kim, Jaeseok
    • Journal of Korea Multimedia Society
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    • v.18 no.7
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    • pp.853-863
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    • 2015
  • In this paper, we proposed cross-layered approach of video codec and communication system for the efficient video streaming service. Conventional video streaming is served by divided system which consist of video codec layer and communication layer. Its disintegration causes the limitation of the performance of video streaming service. With the cross-layered design, each layer could share the information and the service is able to enhance the performance. And we proposed the selective retransmission method in communication system based on the cross-layered system that reflect the information of encoded video data. Selective retransmission method which consider the characteristics of video data improves the performance of video streaming services. We verified the proposed method with raw format full HD test sequence with H.264/AVC codec and MATLAB simulation. The simulation results show that the proposed method improves about 10% PSNR performance.

Hardware Design of LBP Operation for Real-time Face Detection of HD Images (HD 영상의 실시간 얼굴 검출을 위한 LBP 연산의 하드웨어 설계)

  • Noh, Hyun-Jin;Kim, Tae-Wan;Chung, Yum-Mo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.10
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    • pp.67-71
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    • 2011
  • Existing face detection systems, which are used for digital door locks, digital cameras, video surveillance systems, and so on, are software-based implementation for relatively low level resolution images. Therefore, in this case, there are difficulties in detecting faces in a real-time fashion due to the increasing amount of operational processing as well as in allowing the requirements of face detections for HD(High Definition) resolutions. A hardware approach is necessary to efficiently find faces for HD images in real-time embedded systems. This paper proposes and implements a hardware architecture for an LBP(Local Binary Pattern) operation which is a time-consuming part as one of preprocessing steps for face detection. The hardware architecture proposed in this research has been implemented and tested with a FPGA(Field Programmable Gate Array) chip, and shown that the approach guarantees efficient face detection for HD images.