• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8C
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• pp.720-728
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• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of H.2641AVC encoder is greatly increased. Specially, Inter/Intra mode decision method of H.264/AVC using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision considering coding efficiency. From the simulation results, the proposed algorithm reduce the encoding time by maximum 80% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.

• ETRI Journal
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• v.29 no.6
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• pp.826-828
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• 2007

Efficient downscaling in a transcoder is important when the output should be converted to a lower resolution video. In this letter, we suggest an efficient algorithm for transcoding from MPEG-4 SP (with simple profile) to H.264/AVC with spatial downscaling. First, target image blocks are classified into monotonous, complex, and very complex regions for fast mode decision. Second, adaptive search ranges are applied to these image classes for fast motion estimation in an H.264/AVC encoder with predicted motion vectors. Simulation results show that our transcoder considerably reduces transcoding time while video quality is kept almost optimal.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.2
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• pp.77-83
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• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.215-218
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• 2007

여러 동영상 부호화 방식에서 영상프레임을 분할해서 이전에 부호화된 프레임으로부터 움직임을 추정하여 현재의 블록을 예측하는 움직임 보상을 사용하고 있다. 움직임 보상에 사용되는 화소정밀도가 높을수록 보다 좋은 성능을 갖지만 연산량은 증가하게 된다. 본 논문에서는 1/4 화소 정밀도를 지원하는 H.264/AVC 부호화기에 적합한 움직임 보상기를 연구하였다. 전치 배열과 휘도 6-tap 필터 3개를 사용하여 높은 하드웨어 이용률을 갖게하였다. VHDL을 사용하여 Xilinx ISE툴을 사용하여 합성하고, 보드 수준에서 PCI인터페이스를 사용하여 검증하였다. 본 논문에서 제안하는 움직임 보상기는 실시간 처리를 요구하는 분야에 응용 가능할 것으로 예견된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.299-302
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• 2005

요즘 시대는 영상 기술과 IT 발전으로 다양한 멀티미디어 서비스를 제공하기 위해 고품질의 비디오와 높은 데이터 압축을 요구하게 되었고, 이를 위해 MPEG-4 AVC/H.264에서는 기존의 MPEG-4에서 채택한 VLC 기술과 유사한 Context-based Adaptive Variable Length Code(CAVLC)기술을 채택하여 이를 가능하게 하였다. 특히 CAVLC 기술은 HDTV처럼 큰 영상 뿐 아니라 카메라폰이나 DMB등과 같은 영상에서 고품질의 영상을 보다 효율적으로 제공 한다. 본 논문은 최근의 이미지와 비디오 압축에 대한 요구에 따라 H.264/AVC와 MPEG4-PART 1-에서 표준으로 채택한 CAVLC의 부호화 과정을 연구하여 Visual C++언어를 이용한 최적화된 시뮬레이션과 CAVLC의 성능평가를 통한 최적화를 실시하였고, 최적화된 예측 정보를 바탕으로 CAVLC를 VHDL언어를 이용하여 하드웨어로 구현하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.3
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• pp.70-79
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• 2007

H.264/AVC has many repeated computation for motion estimation. Because of that, it takes much time to encode and it is very hard to implement into a real-time encoder. Many fast algorithms were proposed to reduce computation time but encoding quality couldn't be qualified. In this paper we proposed a new motion vector prediction method for efficient and fast full search H.264/AVC motion estimation. We proposed independent motion vector prediction and SAD share for motion estimation. Using our algorithm, motion estimation reduce calculation complexity 80% and less distortion of image (less PSNR drop) than previous full search scheme. We simulated our proposed method. Maximum Y PSNR drop is about 0.04 dB and average bit increasing is about 0.6%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.63-71
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• 2009

In this paper, a new low-complexity distortion estimation method for H.264 rate-distortion optimized mode decision is proposed. The coding processes, such as DCT, quantization, inverse quantization, inverse DCT, and reconstruction are needed to compute the distortion in an H.264 encoder. To reduce these processes, we estimate distortion using integer operations with coefficients obtained in the quantization process. Inverse quantization, inverse DCT, and reconstruction processes are not needed by the proposed method. For quantization parameters 24 to 36, experimental results show that the time saving of rate-distortion optimized mode decision is on average 29 % and as high as 42 % with negligible degradation in coding performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.527-533
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• 2008

Motion compensation always produces the principal bottleneck in the real-time high quality video applications. Therefore, a fast dedicated hardware is needed to perform motion compensation in the real-time video applications. In many video encoding methods, the frames are partitioned into blocks of Pixels. In general, motion compensation predicts present block by estimating the motion from previous frame. In motion compensation, the higher pixel accuracy shows the better performance but the computing complexity is increased. In this paper, we studied an architecture of motion compensator suitable for H.264/AVC encoder that supports quarter-pixel accuracy. The designed motion compensator increases the throughput using transpose array and 3 6-tap Luma filters and efficiently reduces the memory access. The motion compensator is described in VHDL and synthesized in Xilinx ISE and verified using Modelsim_6.1i. Our motion compensator uses 36-tap filters only and performs in 640 clock-cycle per macro block. The motion compensator proposed in this paper is suitable to the areas that require the real-time video processing.

• Journal of Broadcast Engineering
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• v.11 no.1 s.30
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• pp.116-129
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• 2006

The progress of data transmission technology through the Internet has spread a variety of realistic contents. One of such contents is multi-view video that is acquired from multiple camera sensors. In general, the multi-view video processing requires encoders and decoders as many as the number of cameras, and thus the processing complexity results in difficulties of practical implementation. To solve for this problem, this paper considers a simple multi-view system utilizing a single encoder and a single decoder. In the encoder side, input multi-view YUV sequences are combined on GOP units by a video mixer. Then, the mixed sequence is compressed by a single H.264/AVC encoder. The decoding is composed of a single decoder and a scheduler controling the decoding process. The goal of the scheduler is to assign approximately identical number of decoded frames to each view sequence by estimating the decoder utilization of a Gap and subsequently applying frame skip algorithms. Furthermore, in the frame skip, efficient frame selection algorithms are studied for H.264/AVC baseline and main profiles based upon a cost function that is related to perceived video quality. Our proposed method has been performed on various multi-view test sequences adopted by MPEG 3DAV. Experimental results show that approximately identical decoder utilization is achieved for each view sequence so that each view sequence is fairly displayed. As well, the performance of the proposed method is examined in terms of bit-rate and PSNR using a rate-distortion curve.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2285-2291
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• 2011

In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.