• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.77-82
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• 2008

H.264 is a video coding standard of ITU-T and ISO/IEC, and widely spreads its application due to its high compression ratio more than twice that of MPEG-2 and high image quality. It has different architecture depending on demands since it is a lied from small image of QVGA to large size of HD. In this paper, We propose a scalable architecture for intra-prediction of H.264 decoders. The proposed scheme has a scalable architecture that can accommodate up to 4 processing elements depending on performance demands and can reduce the number of access to memory using efficient memory management so as to be energy-efficient. We design the intra-prediction unit using Verilog-HDL and verily it by prototyping using an FPGA. The performance is analyzed using the results of design.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1029-1030
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• 2008

The Scalable Video Coding(SVC) extention of H.264/AVC standard. SVC based temporal, spatial, snd qualty scalability of video bit streams. In this paper, we will develop C-model program and hardware circuits for the chip design of the SVC decoder. In order to acquire the flexibility of the circuit design and reliability of the hardware system development. In these development, we utilize the results of the C-model program to achieve the independencies of each sub-blocks and check the efficiencies of the circuit design results.

• ETRI Journal
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• v.32 no.4
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• pp.626-629
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• 2010

In this letter, we present an enhanced block-based adaptive loop filter (E-BALF) with multiple filter symmetric structures. The E-BALF adapts various filter symmetric structures in a rate-distortion optimization sense, reflecting the statistical properties of each image in a video sequence. Experimental results show that the proposed method achieves a reduction in the Bj${\phi}$ntegaard delta (BD)-bitrate by an average of 9.60% compared with Joint Model 11.0 of H.264/AVC. Compared to the state-of-the-art BALF, a reduction of up to 1.13% in BD-bitrate is achieved.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.991-999
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• 2010

In this paper, we propose a fast motion estimation algorithm for video encoding. Conventional fast motion estimation algorithms have a serious problem of low prediction quality in some frames. However, full search based fast algorithms have low computational reduction ratio. In the paper, we propose an algorithm that significantly reduces unnecessary computations, while keeping prediction quality almost similar to that of the full search. The proposed algorithm uses distribution probability of motion vectors and adaptive search patterns and block matching criteria. By taking different search patterns and error criteria of block matching according to distribution probability of motion vectors, we can reduces only unnecessary computations efficiently. Our algorithm takes only 20~30% in computational amount and has decreased prediction quality about 0~0.02dB compared with the fast full search of the H.264 reference software. Our algorithm will be useful to real-time video coding applications using MPEG-2 or MPEG-4 AVC standards.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.216-225
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• 2011

Following the proliferation of three-dimensional video contents and displays, many terrestrial broadcasting companies have been preparing for stereoscopic 3DTV service. In terrestrial stereoscopic broadcast, it is a difficult task to code and transmit two video sequences while sustaining as high quality as 2DTV broadcast due to the limited bandwidth defined by the existing digital TV standards such as ATSC. Thus, a terrestrial 3DTV broadcasting with a heterogeneous video codec system, where the left image and right images are based on MPEG-2 and H.264/AVC, respectively, is considered in order to achieve both high quality broadcasting service and compatibility for the existing 2DTV viewers. Without significant change in the current terrestrial broadcasting systems, we propose a joint rate control scheme for stereoscopic 3DTV service based on the heterogeneous dual codec systems. The proposed joint rate control scheme applies to the MPEG-2 encoder a quadratic rate-quantization model which is adopted in the H.264/AVC. Then the controller is designed for the sum of the left and right bitstreams to meet the bandwidth requirement of broadcasting standards while the sum of image distortions is minimized by adjusting quantization parameter obtained from the proposed optimization scheme. Besides, we consider a condition on maintaining quality difference between the left and right images around a desired level in the optimization in order to mitigate negative effects on human visual system. Experimental results demonstrate that the proposed bit rate control scheme outperforms the rate control method where each video coding standard uses its own bit rate control algorithm independently in terms of the increase in PSNR by 2.02%, the decrease in the average absolute quality difference by 77.6% and the reduction in the variance of the quality difference by 74.38%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.78-84
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• 2009

In general video coding systems, motion estimation (ME) is regarded as a vital component in a video coder as it consumes a large amount of computation resources. Fractional pixel motion estimation can improve the video compression rate at the cost of higher computational complexity. It is based on the experimental results that the sum of absolute differences (SAD) shows parabolic shape and thus can be approximated by using interpolation technique. In this paper, we propose a fast fractional pixel search algorithm by combining SASR (Simplified Adaptive Search Range) and the CBCDS (Center Biased Cross-Diamond Search) pattern with the predicted motion vector. Compare with the fractional pel full search and the CBFPS, the proposed CBCDS algorithms can reduce fractional pel search points up to 81.4%, respectively with the PSNR lost about 0.05dB.

• Journal of Broadcast Engineering
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• v.13 no.3
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• pp.388-400
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• 2008

This paper introduces a cost-effective method fur improving anchor picture quality of a multiview video coding scheme that is mainly based on chroma compensation. Proposed method is applied to both INTER $16{\times}16$ and SKIP modes in only anchor P-pictures. By testing using JVT common test conditions, simulation results show that proposed method can obtain the average BD-PSNR gains fur U and V as 0.136 dB and 0.127 dB, respectively, while maintaining almost same performance for Y (luminance). For the range of low bit-rates, it is observed that average BD-PSNR gains of Y, U, and V are 0.141 dB, 0.494 dB and 0.525 dB, respectively. Necessary computational complexity is very marginal because the number of anchor P-pictures is only 4.18% in comparison with whole coded sequences, however it can be found that the proposed method can significantly improve the coding efficiencies of color components.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.119-122
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• 2013

ITU-T VCEG 과 ISO/IEC MPEG 이 공동으로 구성한 JCT-VC (Joint Collaborative Team on Video Coding)이 표준화를 진행 중인 HEVC (High Efficiency Video Coding)은 H.264/AVC 대비 약 2 배의 압축효율을 갖는다. 하지만, 계층적 구조를 갖는 가변크기 블록의 사용과 재귀적 부호화 구조에 따른 인코더의 복잡도 증가는 개선해야 할 문제점으로 지적되고 있다. 본 논문에서는 현재 표준화가 진행 중인 HEVC 인코더의 실시간 구현을 위한 SIMD 명령어를 이용한 data-level 병렬화 기법, CPU 및 GPU 를 이용한 multi-threading 기법과 같은 다양한 병렬화 기법을 소개한다. 또한, 이러한 병렬화 기법들을 HEVC 인코더에 적용하기 위해 적합한 연산 및 기능 모듈에 대하여 소개한다. 본 연구를 통하여 HM (HEVC reference model)에 적용한 결과 $832{\times}480$ 영상의 경우 20-30fps 의 부호화 속도를 나타냈으며, $1920{\times}1080$ 영상의 경우 5-10fps 의 부호화 속도를 나타내었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2005.11a
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• pp.25-28
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• 2005

디지틸 멀티미디어 시대를 맞이하여 영상통신 기술이 급속히 발전함에 따라 보다 사실감과 몰입감을 줄 수 있는 3차원 입체 영상처리에 대한 관심이 커지고 있다. 최근 국내외 연구기관에서 다차원 멀티미디어 서비스 개발을 위한 연구가 활발히 진행되고 있으며, MPEG 표준화 그룹에서도 H.264/AVC 압축 방법을 이용한 다시점 비디오 부호화(multi-view video coding, MVC) 방법들이 제안되었다. 본 논문에서는 격자 피라미드 GOP 구조 기반의 다시점 비디오 부호화 방법에 대해 기술하였다. 이 방법은 현재 MPEG 표준화 그룹에서 권고된 ‘Anchor’ 방법에서 고려치 못한 인접 시점간의 공간적인 상관도를 효과적으로 활용하기 위해 격자 GOP구조를 제안했고, 각 시점에 대한 효율적인 부호화를 위해 계층적 피라미드 GOP 구조를 이용하였다. 또한, 공간적인 예측의 경우에 시점간의 전체 변이 (global disparity)를 고려하여 가변적인 탐색 범위를 이용하였다. 본 논문에서 제안한 방법은 현재 MPEG에서 성능 평가의 기준이 되는 ‘Anchor’ 방법에 비해 동일 비트율에서 0.5${\sim}$0.8 dB 정도의 성능 향상을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.