• Journal of Broadcast Engineering
• /
• v.16 no.1
• /
• pp.174-177
• /
• 2011

In this paper, we investigate a method for designing FIR filters with CSD coefficients. Firstly, the H/W complexity of a CSD FIR filter is estimated in terms of number of gates. Using the estimated complexity, an optimal filter that can meet the required performance with minimal H/W complexity can be designed. Next, based on the MILP problem solver called BonsaiG, we present a filter design program. From the two design examples, it is demonstrated that an optimal filter can be obtained by comparing the complexity of the candidate filters in terms of the gate counts, whose differences are estimated to be about 400-600 gates.

• Journal of Broadcast Engineering
• /
• v.9 no.4 s.25
• /
• pp.384-390
• /
• 2004

In this paper we compare the performance of 4 different algorithms for converting the sampling frequency of an audio from 44.1KHz to 48KHz. The algorithms considered here include the basic polyphase method. sine function based method. multi-stage method. and B-spline based method. For a fair comparison, the sampling rate converters using the 4 algorithms are redesigned under a high fidelity condition. Then, their H/W complexities are compared in terms of the computational complexity and the memory size. As a result, it is shown that the basic polyphase method and sine function based method outperform the other two in terms of the computational complexity, while the B-spline based method requires less memory than the others.

• Journal of Communications and Networks
• /
• v.15 no.4
• /
• pp.370-382
• /
• 2013

Distributed massive MIMO systems, which have high bandwidth efficiency and can accommodate a tremendous amount of traffic using algorithms such as zero-forcing beam forming (ZFBF), may be deployed in large public venues with the antennas mounted under-floor. In this case the channel gain matrix H can be modeled as a multi-banded matrix, in which off-diagonal entries decay both exponentially due to heavy human penetration loss and polynomially due to free space propagation loss. To enable practical implementation of such systems, we present a multi-banded matrix inversion algorithm that substantially reduces the complexity of ZFBF by keeping the most significant entries in H and the precoding matrix W. We introduce a parameter p to control the sparsity of H and W and thus achieve the tradeoff between the computational complexity and the system throughput. The proposed algorithm includes dense and sparse precoding versions, providing quadratic and linear complexity, respectively, relative to the number of antennas. We present analysis and numerical evaluations to show that the signal-to-interference ratio (SIR) increases linearly with p in dense precoding. In sparse precoding, we demonstrate the necessity of using directional antennas by both analysis and simulations. When the directional antenna gain increases, the resulting SIR increment in sparse precoding increases linearly with p, while the SIR of dense precoding is much less sensitive to changes in p.

• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.20-22
• /
• 2007

The H.264/AVC standard developed by the joint Video Team (JVT) provides better coding efficiency than previous standards. The new emerging H.264/AVC employs variable block size motion estimation using multiple reference frame with 1/4-pel MV(Motion Vector) accuracy. These techniques are a important feature to accomplish higher coding efficiency. However, these techniques are increased overall computational complexity. To overcome this problem, this paper proposes advanced fast mode decision suited for variable block size by classifying inter mode based on Rate Distortion Optimization(RDO) technique. Proposed algorithm is going to use to implement H/W structure for fast mode decision. The experimental results shows that the proposed algorithm provides significant reduction computational complexity without any noticeable coding loss and additional computation. Entire computational complexity is decreased about 30%.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.45 no.5
• /
• pp.79-86
• /
• 2008

H.264/AVC is the newest international video coding standard developed by the joint ITU-T and ISO/IEC standards organizations. This newest video coding standard offers much higher coding efficiency than the H.261, H.263 and MPEG-4. But it has high computing complexity and high H/W resources wasting problem. This paper described the two unit parallel pipeline structure. This new structure comparing with standard model decreased the computing complexity of 67% and the H/W resources waste of 3%.

• 한국정보통신설비학회:학술대회논문집
• /
• 2008.08a
• /
• pp.218-222
• /
• 2008

RF power amplifier requires linearization in order to reduce adjacent channel interference. And most of the existing linearization algorithms assume that a PA has memory-less nonlinearity. But for the wider bandwidth signal, the memory effect of PA cannot be ignored. This paper investigates digital pre-distortion by use of a memory polynomial model which compensates for amplifier nonlinearity and memory effect. The look-up table based implementation scheme is used to reduce the computational complexity of the pre-distortion block. The linearization performance is demonstrated on wideband CDMA signal and class AB high power amplifier.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.4
• /
• pp.409-416
• /
• 2014

In H/W implementation for the finite field, the use of normal basis has several advantages, especially the optimal normal basis is the most efficient to H/W implementation in $GF(2^m)$. The finite field $GF(2^m)$ with type I optimal normal basis(ONB) has the disadvantage not applicable to some cryptography since m is even. The finite field $GF(2^m)$ with type II ONB, however, such as $GF(2^{233})$ are applicable to ECDSA recommended by NIST. In this paper, we propose a bit-parallel multiplier over $GF(2^m)$ having a type II ONB, which performs multiplication over $GF(2^m)$ in the extension field $GF(2^{2m})$. The time and area complexity of the proposed multiplier is the same as or partially better than the best known type II ONB bit-parallel multiplier.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.5
• /
• pp.153-164
• /
• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Proceedings of the KIPE Conference
• /
• 1998.10a
• /
• pp.855-858
• /
• 1998

Many semiconductive switches are operated in series for high voltage operation. The same number of gate drivers are needed to control all the switches, hence, the drivers cause high cost and system complexity. In this study, a simple and low cost gate driver for high voltage thyristor diode switches is investigated. This gate driver can operate several high voltage thyristor diode switches at the same time.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.589-592
• /
• 2004

The CORDIC algorithm can be implemented very simple H/W, but needs a lot of latency to compute trigonometric function. The RA(Redundant Arithmetic) resolves this problem, but also has difficulty to determine the directions of micro-rotations. The pre-computed direction of micro-rotation algorithm relieves the RA of this matter. In this paper, we proposed the modified the pre-computed algorithm adopted with a table-lookup. Instead of reducing H/W complexity, its performance and calculation errors are improved.