• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1682-1687
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• 2016

Approximately 520thousand elevators are operating now in Korea, about 40% ~ 60% of the elevator power is generated. In this paper, by using the method of adding regeneration power of the elevator to the grid-tied photo voltaic inverter, PV generation that was dependant on the solar radiation was significantly improved. In order to confirm this, the regeneration power of the elevator has been simulated in 12% of the rating load, and measured the regeneration power of the elevator in the actual condition to assess the differences of it. The 5[kW] hybrid grid-tied photo voltaic invertor has been fabricated to conduct an experiment for the confirmation of the proposing method. The effectiveness of the proposing method has been reassured with the result of experiment that include the transfer interface part of the regeneration power of the elevator.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1780-1790
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• 2018

Voltage feed-forward control (VFFC) is widely used in LCL-type grid-tied inverters due to its advantages in terms of disturbance rejection performance and fast dynamic response. However, VFFC may worsen the stability of inverters under weak grid conditions. It is revealed in this paper that a large phase-lag in the low-frequency range is introduced by VFFC, which reduces the phase margin significantly and leads to instability. To address this problem, a novel virtual-impedance-based control, where a phase-lead is introduced into the low-frequency area to compensate for the phase lag caused by VFFC, is proposed to improve system stability. The proposed control is realized with a high-pass filter, without high-order-derivative components. It features easy implementation and good noise immunity. A detailed design procedure for the virtual impedance control is presented. Both theoretical analysis and experimental results verify the effectiveness of the control proposed.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.255-262
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• 2011

This paper proposes a grid-tied power conditioning system for fuel cell, which consists of three-phase current-fed DC-DC converter and three-phase PWM inverter. The three-phase current-fed DC-DC converter boosts fuel cell voltage of 26-48 V up to 400 V with zero-voltage switching (ZVS) scheme, while the three-phase PWM(Pulse Width Modulation) inverter controls the active and reactive power supplied to the grid. The operation of the proposed power conditioning system with fuel cell model is verified through simulations with PSCAD/EMTDC software. The feasibility of hardware implementation is verified through experimental works with a laboratory prototype with 1.2 kW proton exchange membrane (PEM) fuel cell stack. The proposed power conditioning system can be commercialized to interconnect the fuel cell with the power grid.

• Journal of Power Electronics
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• v.11 no.4
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• pp.551-560
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• 2011

This paper proposes a grid-tied power conditioning system for the fuel cell power generation, which consists of a 2-stage DC-DC converter and a 3-phase PWM inverter. The 2-stage DC-DC converter boosts the fuel cell stack voltage of 26-48V up to 400V, using a hard-switching boost converter and a high-frequency unregulated LLC resonant converter. The operation of the proposed power conditioning system was verified through simulations with PSCAD/EMTDC software. Based on the simulation results, a laboratory experimental set-up was built with a 1.2kW PEM fuel-cell stack to verify the feasibility of hardware implementation. The developed power conditioning system shows a high efficiency of 91%, which is a very positive result for the commercialization.

• 한국전산유체공학회:학술대회논문집
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• 2005.10a
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• pp.157-162
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• 2005

Parallel implementation and performance assessment of the grid assembly in a structured chimera grid approach is studied. The grid assembly process, involving hole cutting and searching donor, is parallelized on the PC cluster. A message passing programming model based on the MPI library is implemented using the single program multiple data(SPMD) paradigm. The coarse-grained communication is optimized with the minimized memory allocation because that the parallel grid assembly can access the decomposed geometry data in other processors by only message passing in the distributed memory system such as a PC cluster. The grid assembly workload is based on the static load balancing tied to flow solver. A goal of this work is a development of parallelized grid assembly that is suited for handling multiple moving body problems with large grid size.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.325-333
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• 2021

A 3 kW grid-tied PV inverter with Gallium nitride high-electron mobility transistor (GaN HEMT) for domestic commercialization was developed using boost converter and full-bridge inverter with LCL filter topology. Recently, many GaN HEMTs are manufactured as surface mount packages because of their lower parasitic inductance characteristic than standard TO (transistor outline) packages. A surface mount packaged GaN HEMT releases heat through either top or bottom cooling method. IGOT60R070D1 is selected as a key power semiconductor because it has a top cooling method and fairly low thermal resistances from junction to ambient. Its characteristics allow the design of a 3 kW inverter without forced convection, thereby providing great advantages in terms of easy maintenance and high reliability. 1EDF5673K is selected as a gate driver because its driving current and negative voltage output characteristics are highly optimized for IGOT60R070D1. An LCL filter with passive damping resistor is applied to attenuate the switching frequency harmonics to the grid-tied operation. The designed LCL filter parameters are validated with PSIM simulation. A prototype of 3 kW PV inverter with GaN HEMT is constructed to verify the performance of the power conversion system. It achieved high power density of 614 W/L and peak power efficiency of 99% for the boost converter and inverter.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.6
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• pp.579-586
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• 2013

This paper proposes a mode transition algorithm between the grid-tied and the stand-alone operations for the single-phase inverter with the energy storage system. For the grid-tied operation, the dc-link voltage and the output current are required to be control. For the stand-alone mode, both the output voltage and the output current should be regulated. In order to mitigate a falling-off in control performance during transients in mode change, the load power estimation and the current selection schemes are proposed. The proposed method allows an optimized current reference is selected to reduce an output voltage drop and an excessive over-current in transient. To verify the effectiveness of the proposed method, both the simulation and the experiments for a 3kW single-phase inverter with the energy storage system have been conducted. From the results, it has been confirmed that the proposed method reduces a transient error as well as implementing smooth mode transition.

• Journal of Power Electronics
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• v.13 no.2
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• pp.296-303
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• 2013

This paper proposes a high efficiency three-phase cascaded phase shifted H-bridge multi-level inverter without DC/DC converters for grid-tied multi string photovoltaic (PV) applications. The cascaded H-bridge topology is suitable for PV applications since each PV module can act as a separate DC source for each cascaded H-bridge module. The proposed phase shifted H-bridge multi-level topology offers advantages such as operation at a lower switching frequency and a lower current ripple when compared to conventional two level topologies. It is also shown that low ripple sinusoidal current waveforms are generated with a unity power factor. The control algorithm permits the independent control of each DC link voltage with a maximum power point for each string of PV modules. The use of the controller area network (CAN) communication protocol for H-bridge multi-level inverters, along with localized PWM generation and PV voltage regulation are implemented. It is also shown that the expansion and modularization capabilities of the H-bridge modules are improved since the individual inverter modules operate more independently. The proposed topology is implemented for a three phase 240kW multi-level PV power conditioning system (PCS) which has 40kW H-bridge modules. The experimental results show that the proposed topology has good performance.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.12
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• pp.1848-1856
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• 2012

This paper proposes a new grid-tied power conditioning system for battery energy storage, which is composed of a 2-stage DC-DC converter and a PWM inverter. The 2-stage DC-DC converter is composed of an LLC resonant converter connected in cascade with a 2-quadrant hybrid-switching chopper. The LLC resonant converter operates in constant duty ratio, while the 2-quadrant hybrid-switching chopper operates in variable duty ratio for voltage regulation. The operation of proposed system was verified through theoretical analysis and computer simulations. Based on computer simulations, a hardware prototype was built and tested to confirm the technical feasibility of proposed system. The proposed system could have relatively higher efficiency and smaller size than the existing system.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.